mirror of
https://github.com/openhwgroup/cvw
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
This commit is contained in:
David Harris
commit
d9c16d0726
@ -22,29 +22,109 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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// decode the instruction name, to help the test bench
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module instrNameDecTB(
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module instrNameDecTB #(parameter XLEN) (
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input logic [31:0] instr,
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output string name);
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logic [6:0] op;
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logic funct1;
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logic [1:0] funct2;
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logic [2:0] funct3;
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logic [4:0] funct5;
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logic [6:0] funct7;
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logic [11:0] imm;
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logic [4:0] rs2, rd;
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logic [4:0] rs2, rd, CRrs2;
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logic [1:0] compressedOp;
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logic [5:0] compressed15_10;
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assign op = instr[6:0];
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assign funct1 = instr[6];
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assign funct2 = instr[6:5];
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assign funct3 = instr[14:12];
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assign funct5 = instr[6:2];
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assign funct7 = instr[31:25];
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assign imm = instr[31:20];
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assign rs2 = instr[24:20];
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assign rd = instr[11:7];
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assign compressedOp = instr[1:0];
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assign compressed15_10 = instr[15:10];
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assign CRrs2 = instr[6:2];
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// it would be nice to add the operands to the name
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// create another variable called decoded
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always_comb
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case (compressedOp)
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2'b00:
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casez (compressed15_10)
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6'b000???: if (instr[12:5] != 8'b0) name = "C.ADDI4SPN";
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else if(compressed15_10 == 6'b000000 & op == 7'b0000000 & funct3 == 3'b000) name = "BAD";
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6'b010???: name = "C.LW";
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6'b110???: name = "C.SW";
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6'b011???: if (XLEN == 32'd32) name = "C.FLW";
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else name = "C.LD";
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6'b111???: if (XLEN == 32'd32) name = "C.FSW";
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else name = "C.SD";
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6'b100000: name = "C.LBU";
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6'b100001: if (funct1 == 1'b1) name = "C.LH";
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else if (funct1 == 1'b0) name = "C.LHU";
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6'b100010: name = "C.SB";
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6'b100011: if (funct1 == 1'b0) name = "C.SH";
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6'b001???: name = "C.FLD";
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6'b101???: name = "C.FSD";
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default: name = "ILLEGAL";
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endcase
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2'b01:
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casez (compressed15_10)
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6'b000???: if (instr[12:10] == 3'b0 & rd == 5'b00000 & instr[6:2] == 5'b00000) name = "C.NOP";
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else if (rd != 5'b00000 & instr[6:2] != 5'b00000) name = "C.ADDI";
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6'b010???: if (rd != 5'b00000) name = "C.LI";
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6'b011???: if (rd != 5'b00000 & rd != 5'b00010 & instr[6:2] != 5'b00000) name = "C.LUI";
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else if (rd == 5'b00010 & instr[6:2] != 5'b00000) name = "C.ADDI16SP";
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6'b100?00: name = "C.SRLI";
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6'b100?01: name = "C.SRAI";
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6'b100?10: name = "C.ANDI";
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6'b100011: if (funct2 == 2'b00) name = "C.SUB";
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else if (funct2 == 2'b01) name = "C.XOR";
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else if (funct2 == 2'b10) name = "C.OR";
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else if (funct2 == 2'b11) name = "C.AND";
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6'b101???: name = "C.J";
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6'b110???: name = "C.BEQZ";
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6'b111???: name = "C.BNEZ";
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6'b001???: if (XLEN == 32'd32) name = "C.JAL";
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else if (XLEN == 32'd64 & rd != 5'b00000) name = "C.ADDIW";
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6'b100111: if (XLEN == 32'd64 & funct2 == 2'b00) name = "C.SUBW";
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else if (XLEN == 32'd64 & funct2 == 2'b01) name = "C.ADDW";
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else if (funct5 == 5'b11000) name = "C.ZEXT.B";
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else if (funct5 == 5'b11001) name = "C.SEXT.B";
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else if (funct5 == 5'b11010) name = "C.ZEXT.H";
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else if (funct5 == 5'b11011) name = "C.SEXT.H";
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else if (funct5 == 5'b11101) name = "C.NOT";
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else if (funct2 == 2'b10) name = "C.MUL";
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else if (funct5 == 5'b11100) name = "C.ZEXT.W";
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default: name = "ILLEGAL";
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endcase
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2'b10:
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casez (compressed15_10)
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6'b000???: if (rd != 5'b00000) name = "C.SLLI";
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6'b010???: if (rd != 5'b00000) name = "C.LWSP";
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6'b1000??: if (rd != 5'b00000 & CRrs2 == 5'b00000 ) name = "C.JR";
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else if (rd != 5'b00000 & CRrs2 != 5'b00000 ) name = "C.MV";
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6'b1001??: if (rd == 5'b00000 & CRrs2 == 5'b00000 ) name = "C.EBREAK";
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else if (rd != 5'b00000 & CRrs2 == 5'b00000 ) name = "C.JALR";
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else if (rd != 5'b00000 & CRrs2 != 5'b00000 ) name = "C.ADD";
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6'b110???: name = "C.SWSP";
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6'b011???: if (XLEN == 32'd32) name = "C.FLWSP";
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else if (rd != 5'b00000) name = "C.LDSP";
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6'b111???: if (XLEN == 32'd32) name = "C.FSWSP";
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else name = "C.SDSP";
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6'b001???: name = "C.FLDSP";
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6'b101???: name = "C.FSDSP";
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default: name = "ILLEGAL";
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endcase
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2'b11:
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casez({op, funct3})
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10'b0000000_000: name = "BAD";
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10'b0000011_000: name = "LB";
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10'b0000011_001: name = "LH";
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10'b0000011_010: name = "LW";
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@ -355,4 +435,5 @@ module instrNameDecTB(
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10'b0100111_100: name = "FSQ";
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default: name = "ILLEGAL";
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endcase
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endcase
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endmodule
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@ -19,7 +19,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module instrTrackerTB(
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module instrTrackerTB #(parameter XLEN) (
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input logic clk, reset, FlushE,
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input logic [31:0] InstrF, InstrD,
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input logic [31:0] InstrE, InstrM,
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@ -30,9 +30,9 @@ module instrTrackerTB(
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// stage Instr to Writeback for visualization
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// flopr #(32) InstrWReg(clk, reset, InstrM, InstrW);
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instrNameDecTB fdec(InstrF, InstrFName);
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instrNameDecTB ddec(InstrD, InstrDName);
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instrNameDecTB edec(InstrE, InstrEName);
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instrNameDecTB mdec(InstrM, InstrMName);
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instrNameDecTB wdec(InstrW, InstrWName);
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instrNameDecTB #(XLEN) fdec(InstrF, InstrFName);
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instrNameDecTB #(XLEN) ddec(InstrD, InstrDName);
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instrNameDecTB #(XLEN) edec(InstrE, InstrEName);
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instrNameDecTB #(XLEN) mdec(InstrM, InstrMName);
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instrNameDecTB #(XLEN) wdec(InstrW, InstrWName);
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endmodule
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@ -733,7 +733,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
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int file;
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string LogFile;
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if(`STD_LOG) begin
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instrNameDecTB NameDecoder(rvvi.insn[0][0], instrWName);
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instrNameDecTB #(P.XLEN) NameDecoder(rvvi.insn[0][0], instrWName);
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initial begin
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LogFile = "logs/boottrace.log";
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file = $fopen(LogFile, "w");
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@ -669,7 +669,7 @@ module testbench;
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string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
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logic [31:0] InstrW;
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flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, InstrM, InstrW);
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instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,
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instrTrackerTB #(P.XLEN) it(clk, reset, dut.core.ieu.dp.FlushE,
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dut.core.ifu.InstrRawF[31:0],
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dut.core.ifu.InstrD, dut.core.ifu.InstrE,
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InstrM, InstrW,
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