diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index df3d32f28..65d411839 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -122,7 +122,7 @@ module lsu
   logic [`XLEN-1:0] 	       HPTWReadPTE;
   logic 		       HPTWStall;  
   logic [`XLEN-1:0] 	       HPTWPAdrE;
-  logic [`XLEN-1:0] 	       HPTWPAdrM;  
+//  logic [`XLEN-1:0] 	       HPTWPAdrM;  
   logic [`XLEN-1:0] TranslationVAdr;
   logic [`PA_BITS-1:0] TranslationPAdr;
   logic            UseTranslationVAdr;
@@ -180,7 +180,7 @@ module lsu
     else             assign TranslationPAdrXLEN = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]};
   endgenerate
   mux2 #(`XLEN) HPTWPAdrMux(TranslationPAdrXLEN, TranslationVAdr, UseTranslationVAdr, HPTWPAdrE); // *** misleading to call it PAdr, bad because some bits have been truncated
-  flop #(`XLEN) HPTWPAdrMReg(clk, HPTWPAdrE, HPTWPAdrM);  
+//  flop #(`XLEN) HPTWPAdrMReg(clk, HPTWPAdrE, HPTWPAdrM);  
   
   assign WalkerPageFaultM = WalkerStorePageFaultM | WalkerLoadPageFaultM;
 
@@ -191,7 +191,7 @@ module lsu
 		 .SelPTW(SelPTW),
 		 .HPTWRead(HPTWRead),
 		 .HPTWPAdrE(HPTWPAdrE),
-		 .HPTWPAdrM(HPTWPAdrM),		 
+//		 .HPTWPAdrM(HPTWPAdrM),		 
 		 .HPTWStall(HPTWStall),		 
 		 // CPU connection
 		 .MemRWM(MemRWM),
diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv
index d84c2d603..59193027d 100644
--- a/wally-pipelined/src/lsu/lsuArb.sv
+++ b/wally-pipelined/src/lsu/lsuArb.sv
@@ -33,7 +33,6 @@ module lsuArb
    input logic 		    SelPTW,
    input logic 		    HPTWRead,
    input logic [`XLEN-1:0]  HPTWPAdrE,
-   input logic [`XLEN-1:0]  HPTWPAdrM, 
    output logic 	    HPTWStall, 
 
    // from CPU
@@ -72,6 +71,7 @@ module lsuArb
    );
 
   logic [2:0] PTWSize;
+  logic [`XLEN-1:0]  HPTWPAdrM;
   
   // multiplex the outputs to LSU
   assign DisableTranslation = SelPTW;  // change names between SelPTW would be confusing in DTLB.
@@ -82,6 +82,8 @@ module lsuArb
   endgenerate
   mux2 #(3) sizemux(Funct3M, PTWSize, SelPTW, Funct3MtoDCache);
 
+  flop #(`XLEN) HPTWPAdrMReg(clk, HPTWPAdrE, HPTWPAdrM);   // delay HPTWPAdr by a cycle
+
   assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM;
   assign MemAdrMtoDCache = SelPTW ? HPTWPAdrM : MemAdrM;
   assign MemAdrEtoDCache = SelPTW ? HPTWPAdrE : MemAdrE;  
diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv
index 5dbe4e2b2..d40f2e387 100644
--- a/wally-pipelined/src/mmu/pagetablewalker.sv
+++ b/wally-pipelined/src/mmu/pagetablewalker.sv
@@ -141,6 +141,7 @@ module pagetablewalker
 		assign TranslationPAdr = {PPN, VPN, 3'b000}; 
 	  end
 
+	  // Initial state and misalignment for RV32/64
 	  if (`XLEN == 32) begin
 		assign InitialWalkerState = LEVEL1_SET_ADR;
 		assign TerapageMisaligned = 0; // not applicable