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Verilate running (slowly)

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This commit is contained in:
David Harris 2024-01-07 21:30:33 -08:00
parent 7cd02351d9
commit d93684be21
2 changed files with 32 additions and 15 deletions
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43
sim/verilate
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@ -1,21 +1,42 @@
#!/bin/bash #!/bin/bash
# simulate with Verilator # simulate with Verilator
# verilator -CFLAGS -DVL_DEBUG -CFLAGS -D_GLIBCXX_DEBUG -CFLAGS -ggdb -LDFLAGS -ggdb -CFLAGS -fsanitize=address,undefined -LDFLAGS -fsanitize=address,undefined --timescale "1ns/1ns" --timing --binary --top-module testbench "-I../config/shared" "-I../config/rv64gc" ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv --relative-includes
# verilator -GTEST="\"arch64i\"" --timescale "1ns/1ns" --timing --binary --top-module testbench "-I../config/shared" "-I../config/rv64gc" ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv --relative-includes
export PATH=$PATH:/usr/local/bin/ export PATH=$PATH:/usr/local/bin/
verilator=`which verilator` verilator=`which verilator`
basepath=$(dirname $0)/.. basepath=$(dirname $0)/..
#for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do #for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do
for config in rv64gc; do
echo "$config simulating..." # define associateive array of tests to run
# not working: -GTEST="arch64i" declare -A suites
if !($verilator --timescale "1ns/1ns" --timing --binary "$@" -GTEST="\"arch64i\"" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/testbench.sv $basepath/testbench/common/*.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then rv64gccases=("arch64zba" "arch64zbb" "arch64zbc" "arch64zbs" "arch64i" "arch64m" "arch64a" "arch64f" "arch64d" "arch64c" "arch64f_fma" "arch64d_fma" "wally64priv")
echo "Exiting after $config lint due to errors or warnings" suites["rv64gc"]=${rv64gccases[@]}
exit 1 rv64icases=("arch64i")
fi suites["rv64i"]=${rv32icases[@]}
./obj_dir/Vtestbench rv32gccases=("arch32zba" "arch32zbb" "arch32zbc" "arch32zbs" "arch32i" "arch32m" "arch32a" "arch32f" "arch32d" "arch32c" "arch64f_fma" "arch64d_fma" "wally32priv")
suites["rv32gc"]=${rv32gccases[@]}
rv32imccases=("arch32i" "arch32m" "arch32c")
suites["rv32imc"]=${rv32imccases[@]}
rv32icases=("arch32i")
suites["rv32i"]=${rv32icases[@]}
rv32ecases=("arch32e")
suites["rv32e"]=${rv32ecases[@]}
for config in ${!suites[@]}; do
for suite in ${suites[${config}]}; do
echo "Verilating ${config} ${suite}"
if !($verilator --timescale "1ns/1ns" --timing --binary "$@" -GTEST="\"${suite}\"" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/testbench.sv $basepath/testbench/common/*.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
echo "Exiting after ${config} ${suite} verilation due to errors or warnings"
exit 1
fi
./obj_dir/Vtestbench
done
done done
echo "Verilation complete" echo "Verilation complete"
# command line to invoke Verilator on rv64gc arch64i
# verilator -GTEST="\"arch64i\"" --timescale "1ns/1ns" --timing --binary --top-module testbench "-I../config/shared" "-I../config/rv64gc" ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv --relative-includes
# command line with debugging to address core dumps
# verilator -CFLAGS -DVL_DEBUG -CFLAGS -D_GLIBCXX_DEBUG -CFLAGS -ggdb -LDFLAGS -ggdb -CFLAGS -fsanitize=address,undefined -LDFLAGS -fsanitize=address,undefined --timescale "1ns/1ns" --timing --binary --top-module testbench "-I../config/shared" "-I../config/rv64gc" ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv --relative-includes

4
testbench/testbench.sv
View File

@ -542,10 +542,8 @@ module testbench;
errno = $ferror(fd, errstr); errno = $ferror(fd, errstr);
if (errno != 0) $display("Error %d (code %d) reading line %d of %s: %s", errno, code, siglines, signame, errstr); if (errno != 0) $display("Error %d (code %d) reading line %d of %s: %s", errno, code, siglines, signame, errstr);
if (line.len() > 1) begin // skip blank lines if (line.len() > 1) begin // skip blank lines
// if ($sscanf(line, "%x", sig32[siglines])) siglines = siglines + 1; // increment if line is not blank
if ($sscanf(line, "%x", parsed) != 0) begin if ($sscanf(line, "%x", parsed) != 0) begin
sig32[siglines] = parsed; sig32[siglines] = parsed;
// $display("line = %s len = %d sig32[%d] = %x", line, line.len(), siglines, sig32[siglines]);
siglines = siglines + 1; // increment if line is not blank siglines = siglines + 1; // increment if line is not blank
end end
end end
@ -553,8 +551,6 @@ module testbench;
end end
$fclose(fd); $fclose(fd);
end end
// for(i=0; i<siglines; i++)
// $display("sig32[%d] = %x", i, sig32[i]);
// Check valid number of lines were read // Check valid number of lines were read
if (siglines == 0) begin if (siglines == 0) begin