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Preprocessing cleanup

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This commit is contained in:
David Harris 2022-09-07 10:21:27 -07:00
parent 29f015810b
commit d91b4de348
3 changed files with 4 additions and 8 deletions
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5
pipelined/src/fpu/fdivsqrt.sv
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@ -61,17 +61,16 @@ module fdivsqrt(
logic [`DIVN-2:0] Dpreproc; logic [`DIVN-2:0] Dpreproc;
logic [`DIVb:0] FirstS, FirstSM, FirstQ, FirstQM; logic [`DIVb:0] FirstS, FirstSM, FirstQ, FirstQM;
logic [`DIVb-1:0] FirstC; logic [`DIVb-1:0] FirstC;
logic [`DURLEN-1:0] Dur;
logic NegSticky; logic NegSticky;
logic [`DIVCOPIES-1:0] qn; logic [`DIVCOPIES-1:0] qn;
logic WZero; logic WZero;
fdivsqrtpreproc fdivsqrtpreproc( fdivsqrtpreproc fdivsqrtpreproc(
.clk, .DivStart(DivStartE), .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), .clk, .DivStart(DivStartE), .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE),
.Sqrt(SqrtE), .Dur, .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc); .Sqrt(SqrtE), .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc);
fdivsqrtfsm fdivsqrtfsm( fdivsqrtfsm fdivsqrtfsm(
.reset, .XsE, .SqrtE, .reset, .XsE, .SqrtE,
.Dur, .DivBusy, .clk, .DivStart(DivStartE),.StallE, .StallM, .DivDone, .XZeroE, .YZeroE, .DivBusy, .clk, .DivStart(DivStartE),.StallE, .StallM, .DivDone, .XZeroE, .YZeroE,
.XNaNE, .YNaNE, .XNaNE, .YNaNE,
.XInfE, .YInfE, .EarlyTermShiftE(EarlyTermShiftM), .WZero); .XInfE, .YInfE, .EarlyTermShiftE(EarlyTermShiftM), .WZero);
fdivsqrtiter fdivsqrtiter( fdivsqrtiter fdivsqrtiter(

3
pipelined/src/fpu/fdivsqrtfsm.sv
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@ -41,7 +41,6 @@ module fdivsqrtfsm(
input logic SqrtE, input logic SqrtE,
input logic StallE, input logic StallE,
input logic StallM, input logic StallM,
input logic [`DURLEN-1:0] Dur,
input logic WZero, input logic WZero,
output logic [`DURLEN-1:0] EarlyTermShiftE, output logic [`DURLEN-1:0] EarlyTermShiftE,
output logic DivDone, output logic DivDone,
@ -63,7 +62,7 @@ module fdivsqrtfsm(
if (reset) begin if (reset) begin
state <= #1 IDLE; state <= #1 IDLE;
end else if (DivStart&~StallE) begin end else if (DivStart&~StallE) begin
step <= Dur; step <= (`DURLEN)'(`FPDUR); // *** this should be adjusted to depend on the precision
if (SpecialCase) state <= #1 DONE; if (SpecialCase) state <= #1 DONE;
else state <= #1 BUSY; else state <= #1 BUSY;
end else if (DivDone) begin end else if (DivDone) begin

4
pipelined/src/fpu/fdivsqrtpreproc.sv
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@ -40,8 +40,7 @@ module fdivsqrtpreproc (
input logic XZero, input logic XZero,
output logic [`NE+1:0] QeM, output logic [`NE+1:0] QeM,
output logic [`DIVb:0] X, output logic [`DIVb:0] X,
output logic [`DIVN-2:0] Dpreproc, output logic [`DIVN-2:0] Dpreproc
output logic [`DURLEN-1:0] Dur
); );
// logic [`XLEN-1:0] PosA, PosB; // logic [`XLEN-1:0] PosA, PosB;
// logic [`DIVLEN-1:0] ExtraA, ExtraB, PreprocA, PreprocB, PreprocX, PreprocY; // logic [`DIVLEN-1:0] ExtraA, ExtraB, PreprocA, PreprocB, PreprocX, PreprocY;
@ -73,7 +72,6 @@ module fdivsqrtpreproc (
assign SqrtX = Xe[0]^XZeroCnt[0] ? {1'b0, ~XZero, PreprocX} : {~XZero, PreprocX, 1'b0}; assign SqrtX = Xe[0]^XZeroCnt[0] ? {1'b0, ~XZero, PreprocX} : {~XZero, PreprocX, 1'b0};
assign X = Sqrt ? {SqrtX, {`DIVb-1-`NF{1'b0}}} : {~XZero, PreprocX, {`DIVb-`NF{1'b0}}}; assign X = Sqrt ? {SqrtX, {`DIVb-1-`NF{1'b0}}} : {~XZero, PreprocX, {`DIVb-`NF{1'b0}}};
assign Dpreproc = {PreprocY, {`DIVN-1-`NF{1'b0}}}; assign Dpreproc = {PreprocY, {`DIVN-1-`NF{1'b0}}};
assign Dur = (`DURLEN)'(`FPDUR);
// radix 2 radix 4 // radix 2 radix 4
// 1 copies DIVLEN+2 DIVLEN+2/2 // 1 copies DIVLEN+2 DIVLEN+2/2