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https://github.com/openhwgroup/cvw
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fma passing multiply vectors
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@ -1,10 +1,19 @@
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TARGET ?= fma
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# Makefile
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# for some reason, softfloat.a needs to be symlinked to the local directory. -L isn't working
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CC = gcc
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$(TARGET): $(TARGET).c Makefile
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CFLAGS = -O3
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gcc -O2 -o $(TARGET) $(TARGET).c softfloat.a \
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LIBS = -lm
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-I../../../addins/SoftFloat-3e/source/include \
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LFLAGS = -L.
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-L../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC
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IFLAGS = -I../../../addins/SoftFloat-3e/source/include/
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LIBS = ../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a
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SRCS = $(wildcard *.c)
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PROGS = $(patsubst %.c,%,$(SRCS))
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all: $(PROGS)
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%: %.c
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$(CC) $(CFLAGS) $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS)
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clean:
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clean:
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rm $(TARGET)
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rm -f $(PROGS)
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@ -1,47 +0,0 @@
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#include <stdio.h>
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#include <stdint.h>
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#include "softfloat.h"
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#include "softfloat_types.h"
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int float_rounding_mode = 0;
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union sp {
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unsigned short x[2];
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float y;
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} X;
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int main()
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{
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uint8_t rounding_mode;
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uint8_t exceptions;
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uint32_t multiplier, multiplicand, addend, result;
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float32_t f_multiplier, f_multiplicand, f_addend, f_result;
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multiplier = 0xbf800000;
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multiplicand = 0xbf800000;
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addend = 0xffaaaaaa;
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f_multiplier.v = multiplier;
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f_multiplicand.v = multiplicand;
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f_addend.v = addend;
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softfloat_roundingMode = rounding_mode;
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softfloat_exceptionFlags = 0;
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softfloat_detectTininess = softfloat_tininess_beforeRounding;
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f_result = f32_mulAdd(f_multiplier, f_multiplicand, f_addend);
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result = f_result.v;
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exceptions = softfloat_exceptionFlags & 0x1f;
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printf("%x\n", f_result.v);
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// Print out SP number
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X.x[1] = (f_result.v & 0xffff0000) >> 16;
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X.x[0] = (f_result.v & 0x0000ffff);
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printf("Number = %f\n", X.y);
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return 0;
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}
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@ -13,7 +13,7 @@
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module fma16(
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module fma16(
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input logic [15:0] x, y, z,
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input logic [15:0] x, y, z,
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input logic add, mul, negp, negz,
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input logic mul, add, negp, negz,
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input logic [1:0] roundmode, // 00: rz, 01: rne, 10: rp, 11: rn
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input logic [1:0] roundmode, // 00: rz, 01: rne, 10: rp, 11: rn
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output logic [15:0] result);
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output logic [15:0] result);
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@ -21,12 +21,17 @@ module fma16(
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logic [4:0] xe, ye, ze;
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logic [4:0] xe, ye, ze;
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logic xs, ys, zs;
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logic xs, ys, zs;
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logic zs1; // sign before optional negation
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logic zs1; // sign before optional negation
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logic [21:0] pm;
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logic [5:0] pe;
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logic ps; // sign of product
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logic ps; // sign of product
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logic [22:0] rm;
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logic [6:0] re;
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logic rs;
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unpack unpack(x, y, z, xm, ym, zm, xe, ye, ze, xs, ys, zs1); // unpack inputs
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unpack unpack(x, y, z, xm, ym, zm, xe, ye, ze, xs, ys, zs1); // unpack inputs
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signadj signadj(negp, negz, xs, ys, zs1, ps, zs); // handle negations
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signadj signadj(negp, negz, xs, ys, zs1, ps, zs); // handle negations
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mult mult(mul, xm, ym, xe, ye, pm, pe); // p = x * y
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mult m(mul, xm, ym, xe, ye, pm, pe); // p = x * y
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add add(add, pm, zm, pe, ze, ps, zs, rm, re, rs); // r = z + p
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add a(add, pm, zm, pe, ze, ps, zs, rm, re, rs); // r = z + p
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postproc post(roundmode, rm, re, rs, result); // normalize, round, pack
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postproc post(roundmode, rm, re, rs, result); // normalize, round, pack
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endmodule
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endmodule
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@ -34,13 +39,12 @@ module mult(
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input logic mul,
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input logic mul,
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input logic [10:0] xm, ym,
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input logic [10:0] xm, ym,
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input logic [4:0] xe, ye,
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input logic [4:0] xe, ye,
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input logic xs, ys,
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output logic [21:0] pm,
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output logic [21:0] pm,
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output logic [5:0] pe);
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output logic [5:0] pe);
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// only multiply if mul = 1
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// only multiply if mul = 1
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assign pm = mul ? xm * ym : xm; // multiply mantiassas
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assign pm = mul ? xm * ym : {1'b0, xm, 10'b0}; // multiply mantiassas
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assign pe = mul ? xe + ye : xe;
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assign pe = mul ? xe + ye : {1'b0, xe};
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endmodule
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endmodule
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module add(
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module add(
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@ -58,15 +62,18 @@ module add(
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logic [6:0] are;
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logic [6:0] are;
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logic ars;
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logic ars;
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/*
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alignshift as(pe, ze, zm, zmaligned);
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alignshift as(pe, ze, zm, zmaligned);
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condneg cnp(pm, ps, pmn);
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condneg cnp(pm, ps, pmn);
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condneg cnz(zm, zs, zmn);
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condneg cnz(zm, zs, zmn);
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assign
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*/
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// add or pass product through
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// add or pass product through
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assign rm = add ? arm : pm;
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assign rm = add ? arm : {1'b0, pm};
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assign re = add ? are : pe;
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assign re = add ? are : {1'b0, pe};
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assign rs = add ? ars : ps;
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assign rs = add ? ars : ps;
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);
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endmodule
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module postproc(
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module postproc(
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input logic [1:0] roundmode,
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input logic [1:0] roundmode,
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@ -75,6 +82,33 @@ module postproc(
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input logic rs,
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input logic rs,
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output logic [15:0] result);
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output logic [15:0] result);
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logic [9:0] uf, uff;
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logic [6:0] ue;
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logic [6:0] ueb, uebiased;
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always_comb
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if (rm[21]) begin // normalization right shift by 1 and bump up exponent;
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ue = re + 7'b1;
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uf = rm[20:11];
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end else begin // no normalization shift needed
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ue = re;
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uf = rm[19:10];
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end
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// overflow
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always_comb begin
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ueb = ue-7'd15;
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if (ue >= 7'd46) begin // overflow
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uebiased = 5'd30;
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uff = 10'h3ff;
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end else begin
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uebiased = ue-7'd15;
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uff = uf;
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end
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end
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assign result = {rs, uebiased[4:0], uff};
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// add special case handling for zeros, NaN, Infinity
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// add special case handling for zeros, NaN, Infinity
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endmodule
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endmodule
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@ -107,15 +141,9 @@ module unpacknum(
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logic [9:0] f; // fraction without leading 1
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logic [9:0] f; // fraction without leading 1
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logic [4:0] eb; // biased exponent
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logic [4:0] eb; // biased exponent
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assign {f, eb, s} = num; // pull bit fields out of floating-point number
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assign {s, eb, f} = num; // pull bit fields out of floating-point number
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assign m = {1'b1, f}; // prepend leading 1 to fraction
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assign m = {1'b1, f}; // prepend leading 1 to fraction
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assign e = eb - 15; // remove bias from exponent
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assign e = eb; // leave bias in exponent ***
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endmodule
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endmodule
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// Tests:
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// Every permutation for x, y, z of
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// mantissa = {1.0, 1.0000000001, 1.1, 1.1111111110, 1.1111111111}
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// biased exponent = {1, 2, 14, 15, 16, 21, 29, 30}
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// sign = {0, 1}
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// special case: [normal, 0, INF, NaN]
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#!/usr/bin/python3
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# fma16_testgen.py
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# David_Harris@hmc.edu 26 February 2022
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# Generate test cases for 16-bit FMA
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def makeVal(val):
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def makeCase(x, y, z, mul, add, msg):
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xval = makeVal(x);
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yval = makeVal(y);
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zval = makeVal(z);
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mode = mul*2+add; # convert to hexadecimal code
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expected = makeExpected(x, y, z, mul, add);
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print(xval,"_", yval, "_", zval, "_", mode, "_", expected, " //", msg);
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def makeMulCase(x, y, msg):
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makeCase(x, y, "0", 1, 0, msg)
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################################
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## Main program
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################################
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# Directed cases
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makeMulCase("1", "1", "1 x 1");
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# Corner cases
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# Random cases
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@ -1 +0,0 @@
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../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a
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