From b815f17560004993f80cd529047ed9a4cddc05a4 Mon Sep 17 00:00:00 2001
From: Kevin Kim <kevindkim723@gmail.com>
Date: Tue, 20 Feb 2024 17:16:29 -0800
Subject: [PATCH 1/6] regression-wally handles softfloat

---
 sim/regression-wally | 114 +++++++++++++++++++++++++++++++++++++++----
 1 file changed, 104 insertions(+), 10 deletions(-)

diff --git a/sim/regression-wally b/sim/regression-wally
index d06ac0b28..61f133fa9 100755
--- a/sim/regression-wally
+++ b/sim/regression-wally
@@ -33,6 +33,7 @@ os.chdir(regressionDir)
 coverage = '-coverage' in sys.argv
 fp = '-fp' in sys.argv
 nightly = '-nightly' in sys.argv
+softfloat = '-softfloat' in sys.argv
 
 TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr'])
 # name:     the name of this test configuration (used in printing human-readable
@@ -161,6 +162,45 @@ for test in tests64gc:
 
 # run derivative configurations if requested  
 if (nightly):
+    derivconfigtests = [
+        ["div_2_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
+        ["div_2_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
+        ["div_2_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
+        ["div_2_2i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
+        ["div_2_4_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
+        ["div_2_4i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
+        ["div_4_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
+        ["div_4_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
+        ["div_4_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
+        ["div_4_2i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
+        ["div_4_4_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
+        ["div_4_4i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
+        ["div_2_1_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
+        ["div_2_1i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
+        ["div_2_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
+        ["div_2_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
+        ["div_2_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
+        ["div_2_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
+        ["div_4_1_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
+        ["div_4_1i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
+        ["div_4_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
+        ["div_4_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
+        ["div_4_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
+        ["div_4_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
+
+
+        ["f_rv32gc", ["arch32f", "arch32f_divsqrt"]],
+        ["fh_rv32gc", ["arch32f", "arch32f_divsqrt"]],
+        ["fdh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32d", "arch32d_divsqrt"]],
+        ["fdq_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32d", "arch32d_divsqrt" ]],
+        ["fdqh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32d", "arch32d_divsqrt"]],
+        ["f_rv64gc", ["arch64f", "arch64f_divsqrt"]],
+        ["fh_rv64gc", ["arch64f", "arch64f_divsqrt"]], # hanging 1/31/24 dh; try again when lint is fixed
+        ["fdh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64d", "arch64d_divsqrt"]],
+        ["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64d", "arch64d_divsqrt"]],
+        ["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64d", "arch64d_divsqrt"]],
+    ]
+    """
     derivconfigtests = [
         ["tlb2_rv32gc", ["wally32priv"]],
         ["tlb16_rv32gc", ["wally32priv"]],
@@ -269,16 +309,16 @@ if (nightly):
 
 
 #  enable floating-point tests when lint is fixed
-#        ["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma"]],
-#        ["fh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32zfh", "arch32zfh_divsqrt"]],
-#        ["fdh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]],
-#        ["fdq_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]],
-#        ["fdqh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]],
-#        ["f_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma"]],
-#        ["fh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64zfh", "arch64zfh_divsqrt"]], # hanging 1/31/24 dh; try again when lint is fixed
-#        ["fdh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]],
-#        ["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]],
-#        ["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]],
+        ["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma"]],
+        ["fh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32zfh", "arch32zfh_divsqrt"]],
+        ["fdh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]],
+        ["fdq_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]],
+        ["fdqh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]],
+        ["f_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma"]],
+        ["fh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64zfh", "arch64zfh_divsqrt"]], # hanging 1/31/24 dh; try again when lint is fixed
+        ["fdh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]],
+        ["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]],
+        ["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]],
         
 
     ]
@@ -309,6 +349,58 @@ for test in tests32e:
         grepstr="All tests ran without failures")
   configs.append(tc)
 
+
+# softfloat tests
+if (softfloat):
+    configs = []
+    softfloatconfigs = ['fdh_ieee_rv32gc', 'fdqh_ieee_rv32gc', 'fdq_ieee_rv32gc', \
+    'fh_ieee_v32gc', 'f_ieee_rv64gc', 'fdqh_ieee_rv64gc', \
+    'fdq_ieee_rv64gc', 'div_2_1_rv32gc', 'div_2_2_rv32gc', \
+    'div_2_4_rv32gc', 'div_4_1_rv32gc', 'div_4_2_rv32gc', \
+    'div_4_4_rv32gc', 'fd_ieee_rv32gc', 'fh_ieee_rv32gc', \
+    'div_2_1_rv64gc', 'div_2_2_rv64gc', 'div_2_4_rv64gc', \
+    'div_4_1_rv64gc', 'div_4_2_rv64gc', 'div_4_4_rv64gc', \
+    'fd_ieee_rv64gc', 'fh_ieee_rv64gc', 'f_ieee_rv32gc']
+    for config in softfloatconfigs:
+        # div test case
+        divtest = TestCase(
+            name="div",
+            variant=config,
+            cmd="vsim > {} -c  <<!\ndo testfloat.do " + config + " div \n!",
+            grepstr="All Tests completed with          0 errors"
+        )
+        configs.append(divtest)
+
+        # sqrt test case
+        sqrttest = TestCase(
+            name="sqrt",
+            variant=config,
+            cmd="vsim > {} -c  <<!\ndo testfloat.do " + config + " sqrt \n!",
+            grepstr="All Tests completed with          0 errors"
+        )
+        configs.append(sqrttest)
+
+        # skip if divider variant config
+        if ("ieee" in config[0]):
+            # cvtint test case
+            cvtinttest = TestCase(
+                name="cvtint",
+                variant=config,
+                cmd="vsim > {} -c  <<!\ndo testfloat.do " + config + " cvtint \n!",
+                grepstr="All Tests completed with          0 errors"
+                )
+            configs.append(cvtinttest)
+
+            # cvtfp test case
+            cvtfptest = TestCase(
+                name="cvtfp",
+                variant=config,
+                cmd="vsim > {} -c  <<!\ndo testfloat.do " + config + " cvtfp \n!",
+                grepstr="All Tests completed with          0 errors"
+            )
+            configs.append(cvtfptest)    
+      
+
     
 
 import os
@@ -368,6 +460,8 @@ def main():
     elif '-nightly' in sys.argv:
         TIMEOUT_DUR = 60*1440 # 1 day
         configs.append(getBuildrootTC(boot=False))
+    elif '-softfloat' in sys.argv:
+        TIMEOUT_DUR = 60*60 # seconds
     else:
         TIMEOUT_DUR = 10*60 # seconds
         configs.append(getBuildrootTC(boot=False))

From 2b662565d7b6e2d4046337e86efa1feeca5b379c Mon Sep 17 00:00:00 2001
From: Kevin Kim <kevindkim723@gmail.com>
Date: Tue, 20 Feb 2024 17:17:45 -0800
Subject: [PATCH 2/6] typo fix

---
 sim/regression-wally | 1 -
 1 file changed, 1 deletion(-)

diff --git a/sim/regression-wally b/sim/regression-wally
index 61f133fa9..b721d8899 100755
--- a/sim/regression-wally
+++ b/sim/regression-wally
@@ -200,7 +200,6 @@ if (nightly):
         ["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64d", "arch64d_divsqrt"]],
         ["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64d", "arch64d_divsqrt"]],
     ]
-    """
     derivconfigtests = [
         ["tlb2_rv32gc", ["wally32priv"]],
         ["tlb16_rv32gc", ["wally32priv"]],

From c8ff1bddec4bb87aae060c9b9da6094871bff55b Mon Sep 17 00:00:00 2001
From: Kevin Kim <kevindkim723@gmail.com>
Date: Tue, 20 Feb 2024 17:21:29 -0800
Subject: [PATCH 3/6] formatting

---
 addins/riscv-arch-test | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test
index 8a52b016d..c955abf75 160000
--- a/addins/riscv-arch-test
+++ b/addins/riscv-arch-test
@@ -1 +1 @@
-Subproject commit 8a52b016dbe1e2733cc168b9d6e5c93e39059d4d
+Subproject commit c955abf757df98cf38809e40a62d2a6b448ea507

From 7e3df23f28c202a8eaf0aaa67e539e1c32c45fc4 Mon Sep 17 00:00:00 2001
From: Kevin Kim <kevindkim723@gmail.com>
Date: Tue, 20 Feb 2024 17:24:04 -0800
Subject: [PATCH 4/6] Revert "formatting"

This reverts commit c8ff1bddec4bb87aae060c9b9da6094871bff55b.
---
 addins/riscv-arch-test | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test
index c955abf75..8a52b016d 160000
--- a/addins/riscv-arch-test
+++ b/addins/riscv-arch-test
@@ -1 +1 @@
-Subproject commit c955abf757df98cf38809e40a62d2a6b448ea507
+Subproject commit 8a52b016dbe1e2733cc168b9d6e5c93e39059d4d

From 19a61e301ea4a1aea3382225b6fdd017c054d088 Mon Sep 17 00:00:00 2001
From: Kevin Kim <kevindkim723@gmail.com>
Date: Tue, 20 Feb 2024 17:24:15 -0800
Subject: [PATCH 5/6] formatting

---
 sim/regression-wally | 39 ---------------------------------------
 1 file changed, 39 deletions(-)

diff --git a/sim/regression-wally b/sim/regression-wally
index b721d8899..28c2e9a7a 100755
--- a/sim/regression-wally
+++ b/sim/regression-wally
@@ -162,44 +162,6 @@ for test in tests64gc:
 
 # run derivative configurations if requested  
 if (nightly):
-    derivconfigtests = [
-        ["div_2_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
-        ["div_2_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
-        ["div_2_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
-        ["div_2_2i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
-        ["div_2_4_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
-        ["div_2_4i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
-        ["div_4_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
-        ["div_4_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
-        ["div_4_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
-        ["div_4_2i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
-        ["div_4_4_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
-        ["div_4_4i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
-        ["div_2_1_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
-        ["div_2_1i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
-        ["div_2_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
-        ["div_2_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
-        ["div_2_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
-        ["div_2_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
-        ["div_4_1_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
-        ["div_4_1i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
-        ["div_4_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
-        ["div_4_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
-        ["div_4_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
-        ["div_4_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
-
-
-        ["f_rv32gc", ["arch32f", "arch32f_divsqrt"]],
-        ["fh_rv32gc", ["arch32f", "arch32f_divsqrt"]],
-        ["fdh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32d", "arch32d_divsqrt"]],
-        ["fdq_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32d", "arch32d_divsqrt" ]],
-        ["fdqh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32d", "arch32d_divsqrt"]],
-        ["f_rv64gc", ["arch64f", "arch64f_divsqrt"]],
-        ["fh_rv64gc", ["arch64f", "arch64f_divsqrt"]], # hanging 1/31/24 dh; try again when lint is fixed
-        ["fdh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64d", "arch64d_divsqrt"]],
-        ["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64d", "arch64d_divsqrt"]],
-        ["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64d", "arch64d_divsqrt"]],
-    ]
     derivconfigtests = [
         ["tlb2_rv32gc", ["wally32priv"]],
         ["tlb16_rv32gc", ["wally32priv"]],
@@ -306,7 +268,6 @@ if (nightly):
         ["bpred_GSHARE_10_10_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
         ["bpred_GSHARE_10_10_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
 
-
 #  enable floating-point tests when lint is fixed
         ["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma"]],
         ["fh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32zfh", "arch32zfh_divsqrt"]],

From 02081cac409fec665c0ed0de29648f8dbbca4fb4 Mon Sep 17 00:00:00 2001
From: Kevin Kim <kevindkim723@gmail.com>
Date: Wed, 21 Feb 2024 20:49:38 -0800
Subject: [PATCH 6/6] softfloat jobs now run concurrently with help of
 testfloat-batch.do directing compiled designs into individual folders for
 each config/test

---
 sim/regression-wally   | 15 +++++++-----
 sim/testfloat-batch.do | 55 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 64 insertions(+), 6 deletions(-)
 create mode 100644 sim/testfloat-batch.do

diff --git a/sim/regression-wally b/sim/regression-wally
index 28c2e9a7a..e53ebd0d8 100755
--- a/sim/regression-wally
+++ b/sim/regression-wally
@@ -326,7 +326,7 @@ if (softfloat):
         divtest = TestCase(
             name="div",
             variant=config,
-            cmd="vsim > {} -c  <<!\ndo testfloat.do " + config + " div \n!",
+            cmd="vsim > {} -c  <<!\ndo testfloat-batch.do " + config + " div \n!",
             grepstr="All Tests completed with          0 errors"
         )
         configs.append(divtest)
@@ -335,27 +335,30 @@ if (softfloat):
         sqrttest = TestCase(
             name="sqrt",
             variant=config,
-            cmd="vsim > {} -c  <<!\ndo testfloat.do " + config + " sqrt \n!",
+            cmd="vsim > {} -c  <<!\ndo testfloat-batch.do " + config + " sqrt \n!",
             grepstr="All Tests completed with          0 errors"
         )
-        configs.append(sqrttest)
+        #configs.append(sqrttest)
+        configs.insert(0,sqrttest)
+
 
         # skip if divider variant config
-        if ("ieee" in config[0]):
+        if ("ieee" in config):
             # cvtint test case
             cvtinttest = TestCase(
                 name="cvtint",
                 variant=config,
-                cmd="vsim > {} -c  <<!\ndo testfloat.do " + config + " cvtint \n!",
+                cmd="vsim > {} -c  <<!\ndo testfloat-batch.do " + config + " cvtint \n!",
                 grepstr="All Tests completed with          0 errors"
                 )
             configs.append(cvtinttest)
 
             # cvtfp test case
+            # WILL fail on F_only (cvtfp converts from one fpsize to another. refer to spec)
             cvtfptest = TestCase(
                 name="cvtfp",
                 variant=config,
-                cmd="vsim > {} -c  <<!\ndo testfloat.do " + config + " cvtfp \n!",
+                cmd="vsim > {} -c  <<!\ndo testfloat-batch.do " + config + " cvtfp \n!",
                 grepstr="All Tests completed with          0 errors"
             )
             configs.append(cvtfptest)    
diff --git a/sim/testfloat-batch.do b/sim/testfloat-batch.do
new file mode 100644
index 000000000..f20867ddc
--- /dev/null
+++ b/sim/testfloat-batch.do
@@ -0,0 +1,55 @@
+# testfloat-batch.do 
+#
+# Modification by Oklahoma State University & Harvey Mudd College
+# Use with Testbench 
+# James Stine, 2008; David Harris 2021; Kevin Kim 2024
+# Go Cowboys!!!!!!
+#
+# Takes 1:10 to run RV64IC tests using gui
+
+# run with vsim -do "do wally.do rv64ic riscvarchtest-64m"
+
+onbreak {resume}
+
+# create library
+
+if [file exists wkdir/work_${1}_${2}] {
+    vdel -lib wkdir/work_${1}_${2} -all
+}
+vlib wkdir/work_${1}_${2}
+
+
+
+# c# compile source files
+# suppress spurious warnngs about 
+# "Extra checking for conflicts with always_comb done at vopt time"
+# because vsim will run vopt
+
+# start and run simulation
+# remove +acc flag for faster sim during regressions if there is no need to access internal signals
+# $num = the added words after the call
+
+vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv  ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697,7033 
+
+
+# Set WAV variable to avoid having any output to wave (to limit disk space)
+quietly set WAV 0;
+
+# Determine if nowave argument is provided this removes any output to
+# a wlf or wave window to reduce disk space.
+if {$WAV eq 0} {
+    puts "No wave output is selected"
+} else {
+    puts "wave output is selected"
+    view wave
+    add log -recursive /*
+    do wave-fpu.do    
+}  
+
+# Change TEST_SIZE to only test certain FP width
+# values are QP, DP, SP, HP or all for all tests
+
+vopt +acc wkdir/work_${1}_${2}.testbenchfp -work wkdir/work_${1}_${2} -G TEST=$2 -G TEST_SIZE="all" -o testbenchopt
+vsim -lib wkdir/work_${1}_${2} testbenchopt  -fatal 7 -suppress 3829
+#-- Run the Simulation 
+run -all