From d901f60a6dd3a0fd3fa61d6039b332783d4eb0de Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Thu, 16 Sep 2021 16:56:48 -0500
Subject: [PATCH] Added flush controls to cachway.

---
 wally-pipelined/src/cache/cacheway.sv  | 5 ++++-
 wally-pipelined/src/cache/dcache.sv    | 9 ++++++++-
 wally-pipelined/src/cache/dcachefsm.sv | 4 +++-
 wally-pipelined/src/cache/icache.sv    | 2 ++
 4 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/wally-pipelined/src/cache/cacheway.sv b/wally-pipelined/src/cache/cacheway.sv
index af6076eaa..8b6492ee8 100644
--- a/wally-pipelined/src/cache/cacheway.sv
+++ b/wally-pipelined/src/cache/cacheway.sv
@@ -43,6 +43,8 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
    input logic 			      SelEvict,
    input logic 			      VictimWay,
    input logic 			      InvalidateAll,
+   input logic 			      SelFlush,
+   input logic 			      FlushWay,
 
    output logic [BLOCKLEN-1:0] 	      ReadDataBlockWayMasked,
    output logic 		      WayHit,
@@ -80,7 +82,8 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
 	      .WriteEnable(TagWriteEnable));
 
   assign WayHit = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]);
-  assign SelectedWay = SelEvict ? VictimWay : WayHit;  
+  assign SelectedWay = SelFlush ? FlushWay : 
+		       SelEvict ? VictimWay : WayHit;  
   assign ReadDataBlockWayMasked = SelectedWay ? ReadDataBlockWay : '0;  // first part of AO mux.
 
   assign VictimDirtyWay = VictimWay & Dirty & Valid;
diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv
index 9ed642c17..31130d387 100644
--- a/wally-pipelined/src/cache/dcache.sv
+++ b/wally-pipelined/src/cache/dcache.sv
@@ -125,6 +125,9 @@ module dcache
   logic [TAGLEN-1:0] 	       VictimTagWay [NUMWAYS-1:0];
   logic [TAGLEN-1:0] 	       VictimTag;
 
+  logic [INDEXLEN-1:0] 	       FlushAdr;
+  logic [NUMWAYS-1:0] 	       FlushWay;
+  logic 		       SelFlush;
   
   logic AnyCPUReqM;
   logic FetchCountFlag;
@@ -137,10 +140,11 @@ module dcache
   
   // Read Path CPU (IEU) side
 
-  mux3 #(INDEXLEN)
+  mux4 #(INDEXLEN)
   AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
 	    .d1(VAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
 	    .d2(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
+	    .d3(FlushAdr),
 	    .s(SelAdrM),
 	    .y(RAdr));
 
@@ -160,6 +164,8 @@ module dcache
 		      .ClearDirty,
 		      .SelEvict,
 		      .VictimWay,
+		      .FlushWay,
+		      .SelFlush,
 		      .ReadDataBlockWayMasked(ReadDataBlockWayMaskedM),
 		      .WayHit,
 		      .VictimDirtyWay,
@@ -334,6 +340,7 @@ module dcache
 		      .CntReset,
 		      .SelUncached,
 		      .SelEvict,
+		      .SelFlush,
 		      .LRUWriteEn);
   
 
diff --git a/wally-pipelined/src/cache/dcachefsm.sv b/wally-pipelined/src/cache/dcachefsm.sv
index afccb7869..b7296441b 100644
--- a/wally-pipelined/src/cache/dcachefsm.sv
+++ b/wally-pipelined/src/cache/dcachefsm.sv
@@ -77,7 +77,8 @@ module dcachefsm
    output logic      CntReset,
    output logic      SelUncached,
    output logic      SelEvict,
-   output logic      LRUWriteEn
+   output logic      LRUWriteEn,
+   output logic      SelFlush
    );
   
   logic 	     PreCntEn;
@@ -168,6 +169,7 @@ module dcachefsm
     DCacheMiss = 1'b0;
     LRUWriteEn = 1'b0;
     MemAfterIWalkDone = 1'b0;
+    SelFlush = 1'b0;
     NextState = STATE_READY;
 
     case (CurrState)
diff --git a/wally-pipelined/src/cache/icache.sv b/wally-pipelined/src/cache/icache.sv
index 0e7d0888f..07c458e61 100644
--- a/wally-pipelined/src/cache/icache.sv
+++ b/wally-pipelined/src/cache/icache.sv
@@ -152,6 +152,8 @@ module icache
 		      .ClearDirty(1'b0),
 		      .SelEvict(1'b0),
 		      .VictimWay,
+		      .FlushWay(1'b0),
+		      .SelFlush(1'b0),
 		      .ReadDataBlockWayMasked,
 		      .WayHit,
 		      .VictimDirtyWay(),