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Matthew 2024-06-04 12:11:11 -05:00
parent 5b50fcd4f4
commit d900f68acd
4 changed files with 61 additions and 72 deletions
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82
config/shared/debug.vh
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@ -147,54 +147,54 @@
// 0xc000 – 0xffff | Reserved for non-standard extensions and internal use. // 0xc000 – 0xffff | Reserved for non-standard extensions and internal use.
// privileged/csr/csrm // privileged/csr/csrm
`define MISA 16'h0301 // XLEN P.ZICSR_SUPPORTED (Read Only) `define MISA_REGNO 16'h0301 // XLEN P.ZICSR_SUPPORTED (Read Only)
// wallypipelinedcore // wallypipelinedcore
`define TRAPM 16'hC000 // 1'b P.ZICSR_SUPPORTED (Read Only) `define TRAPM_REGNO 16'hC000 // 1'b P.ZICSR_SUPPORTED (Read Only)
// src/ifu // src/ifu
`define PCM 16'hC001 // XLEN P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED `define PCM_REGNO 16'hC001 // XLEN P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED
`define INSTRM 16'hC002 // 32'b P.ZICSR_SUPPORTED | P.A_SUPPORTED `define INSTRM_REGNO 16'hC002 // 32'b P.ZICSR_SUPPORTED | P.A_SUPPORTED
// ieu/controller // ieu/controller
`define MEMRWM 16'hC003 // 2'b `define MEMRWM_REGNO 16'hC003 // 2'b
`define INSTRVALIDM 16'hC004 // 1'b `define INSTRVALIDM_REGNO 16'hC004 // 1'b
// ieu/datapath // ieu/datapath
`define WRITEDATAM 16'hC005 // XLEN `define WRITEDATAM_REGNO 16'hC005 // XLEN
// lsu // lsu
`define IEUADRM 16'hC006 // XLEN `define IEUADRM_REGNO 16'hC006 // XLEN
`define READDATAM 16'hC007 // LLEN (Read Only) `define READDATAM_REGNO 16'hC007 // LLEN (Read Only)
// src/ieu/datapath // src/ieu/datapath
`define X0 16'h1000 `define X0_REGNO 16'h1000
`define X1 16'h1001 `define X1_REGNO 16'h1001
`define X2 16'h1002 `define X2_REGNO 16'h1002
`define X3 16'h1003 `define X3_REGNO 16'h1003
`define X4 16'h1004 `define X4_REGNO 16'h1004
`define X5 16'h1005 `define X5_REGNO 16'h1005
`define X6 16'h1006 `define X6_REGNO 16'h1006
`define X7 16'h1007 `define X7_REGNO 16'h1007
`define X8 16'h1008 `define X8_REGNO 16'h1008
`define X9 16'h1009 `define X9_REGNO 16'h1009
`define X10 16'h100A `define X10_REGNO 16'h100A
`define X11 16'h100B `define X11_REGNO 16'h100B
`define X12 16'h100C `define X12_REGNO 16'h100C
`define X13 16'h100D `define X13_REGNO 16'h100D
`define X14 16'h100E `define X14_REGNO 16'h100E
`define X15 16'h100F `define X15_REGNO 16'h100F
`define X16 16'h1010 // E_SUPPORTED `define X16_REGNO 16'h1010 // E_SUPPORTED
`define X17 16'h1011 // E_SUPPORTED `define X17_REGNO 16'h1011 // E_SUPPORTED
`define X18 16'h1012 // E_SUPPORTED `define X18_REGNO 16'h1012 // E_SUPPORTED
`define X19 16'h1013 // E_SUPPORTED `define X19_REGNO 16'h1013 // E_SUPPORTED
`define X20 16'h1014 // E_SUPPORTED `define X20_REGNO 16'h1014 // E_SUPPORTED
`define X21 16'h1015 // E_SUPPORTED `define X21_REGNO 16'h1015 // E_SUPPORTED
`define X22 16'h1016 // E_SUPPORTED `define X22_REGNO 16'h1016 // E_SUPPORTED
`define X23 16'h1017 // E_SUPPORTED `define X23_REGNO 16'h1017 // E_SUPPORTED
`define X24 16'h1018 // E_SUPPORTED `define X24_REGNO 16'h1018 // E_SUPPORTED
`define X25 16'h1019 // E_SUPPORTED `define X25_REGNO 16'h1019 // E_SUPPORTED
`define X26 16'h101A // E_SUPPORTED `define X26_REGNO 16'h101A // E_SUPPORTED
`define X27 16'h101B // E_SUPPORTED `define X27_REGNO 16'h101B // E_SUPPORTED
`define X28 16'h101C // E_SUPPORTED `define X28_REGNO 16'h101C // E_SUPPORTED
`define X29 16'h101D // E_SUPPORTED `define X29_REGNO 16'h101D // E_SUPPORTED
`define X30 16'h101E // E_SUPPORTED `define X30_REGNO 16'h101E // E_SUPPORTED
`define X31 16'h101F // E_SUPPORTED `define X31_REGNO 16'h101F // E_SUPPORTED
// ACCESS_MEMORY Control ranges (Not implemented) // ACCESS_MEMORY Control ranges (Not implemented)
//`define AAMVIRTUAL 23 //`define AAMVIRTUAL 23

28
src/debug/rad.sv
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@ -87,29 +87,29 @@ module rad import cvw::*; #(parameter cvw_t P) (
InvalidRegNo = ~P.E_SUPPORTED; InvalidRegNo = ~P.E_SUPPORTED;
GPRRegNo = 1; GPRRegNo = 1;
end end
`MISA : begin `MISA_REGNO : begin
ShiftCount = SCANCHAINLEN - MISA_IDX; ShiftCount = SCANCHAINLEN - MISA_IDX;
InvalidRegNo = ~P.ZICSR_SUPPORTED; InvalidRegNo = ~P.ZICSR_SUPPORTED;
RegReadOnly = 1; RegReadOnly = 1;
end end
`TRAPM : begin `TRAPM_REGNO : begin
ShiftCount = SCANCHAINLEN - TRAPM_IDX; ShiftCount = SCANCHAINLEN - TRAPM_IDX;
InvalidRegNo = ~P.ZICSR_SUPPORTED; InvalidRegNo = ~P.ZICSR_SUPPORTED;
RegReadOnly = 1; RegReadOnly = 1;
end end
`PCM : begin `PCM_REGNO : begin
ShiftCount = SCANCHAINLEN - PCM_IDX; ShiftCount = SCANCHAINLEN - PCM_IDX;
InvalidRegNo = ~(P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED); InvalidRegNo = ~(P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED);
end end
`INSTRM : begin `INSTRM_REGNO : begin
ShiftCount = SCANCHAINLEN - INSTRM_IDX; ShiftCount = SCANCHAINLEN - INSTRM_IDX;
InvalidRegNo = ~(P.ZICSR_SUPPORTED | P.A_SUPPORTED); InvalidRegNo = ~(P.ZICSR_SUPPORTED | P.A_SUPPORTED);
end end
`MEMRWM : ShiftCount = SCANCHAINLEN - MEMRWM_IDX; `MEMRWM_REGNO : ShiftCount = SCANCHAINLEN - MEMRWM_IDX;
`INSTRVALIDM : ShiftCount = SCANCHAINLEN - INSTRVALIDM_IDX; `INSTRVALIDM_REGNO : ShiftCount = SCANCHAINLEN - INSTRVALIDM_IDX;
`WRITEDATAM : ShiftCount = SCANCHAINLEN - WRITEDATAM_IDX; `WRITEDATAM_REGNO : ShiftCount = SCANCHAINLEN - WRITEDATAM_IDX;
`IEUADRM : ShiftCount = SCANCHAINLEN - IEUADRM_IDX; `IEUADRM_REGNO : ShiftCount = SCANCHAINLEN - IEUADRM_IDX;
`READDATAM : begin `READDATAM_REGNO : begin
ShiftCount = SCANCHAINLEN - READDATAM_IDX; ShiftCount = SCANCHAINLEN - READDATAM_IDX;
RegReadOnly = 1; RegReadOnly = 1;
end end
@ -124,11 +124,11 @@ module rad import cvw::*; #(parameter cvw_t P) (
always_comb begin always_comb begin
Mask = 0; Mask = 0;
case(Regno) case(Regno)
`TRAPM : Mask = {1{1'b1}}; `TRAPM_REGNO : Mask = {1{1'b1}};
`INSTRM : Mask = {32{1'b1}}; `INSTRM_REGNO : Mask = {32{1'b1}};
`MEMRWM : Mask = {2{1'b1}}; `MEMRWM_REGNO : Mask = {2{1'b1}};
`INSTRVALIDM : Mask = {1{1'b1}}; `INSTRVALIDM_REGNO : Mask = {1{1'b1}};
`READDATAM : Mask = {P.LLEN{1'b1}}; `READDATAM_REGNO : Mask = {P.LLEN{1'b1}};
default : Mask = {P.XLEN{1'b1}}; default : Mask = {P.XLEN{1'b1}};
endcase endcase
end end

13
src/generic/flop/flopenrcs.sv
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@ -35,21 +35,14 @@ module flopenrcs #(parameter WIDTH = 8) (
); );
logic [WIDTH-1:0] dmux; logic [WIDTH-1:0] dmux;
assign dmux[WIDTH-1] = scan ? scanin : d[WIDTH-1]; mux2 #(1) mux (.y(dmux[WIDTH-1]), .s(scan), .d1(scanin), .d0(d[WIDTH-1]));
assign scanout = q[0]; assign scanout = q[0];
genvar i; genvar i;
for (i=0; i<WIDTH-1; i=i+1) begin for (i=0; i<WIDTH-1; i=i+1) begin
assign dmux[i] = scan ? q[i+1] : d[i]; mux2 #(1) mux (.y(dmux[i]), .s(scan), .d1(q[i+1]), .d0(d[i]));
end end
always_ff @(posedge clk) flopenrc #(WIDTH) flop (.clk, .reset, .clear, .en(en | scan), .d(dmux), .q(q));
if (reset)
q <= '0;
else if (en || scan)
if (clear)
q <= '0;
else
q <= dmux;
endmodule endmodule

10
src/generic/flop/flopenrs.sv
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@ -35,18 +35,14 @@ module flopenrs #(parameter WIDTH = 8) (
); );
logic [WIDTH-1:0] dmux; logic [WIDTH-1:0] dmux;
assign dmux[WIDTH-1] = scan ? scanin : d[WIDTH-1]; mux2 #(1) mux (.y(dmux[WIDTH-1]), .s(scan), .d1(scanin), .d0(d[WIDTH-1]));
assign scanout = q[0]; assign scanout = q[0];
genvar i; genvar i;
for (i=0; i<WIDTH-1; i=i+1) begin for (i=0; i<WIDTH-1; i=i+1) begin
assign dmux[i] = scan ? q[i+1] : d[i]; mux2 #(1) mux (.y(dmux[i]), .s(scan), .d1(q[i+1]), .d0(d[i]));
end end
always_ff @(posedge clk) flopenr #(WIDTH) flop (.clk, .reset, .en(en | scan), .d(dmux), .q(q));
if (reset)
q <= '0;
else if (en || scan)
q <= dmux;
endmodule endmodule