diff --git a/sim/wally-batch.do b/sim/wally-batch.do index 29d31bd25..df34aa0b3 100644 --- a/sim/wally-batch.do +++ b/sim/wally-batch.do @@ -58,15 +58,15 @@ if {$argc >= 3} { # default to config/rv64ic, but allow this to be overridden at the command line. For example: # do wally-pipelined-batch.do ../config/rv32imc rv32imc -if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { +if {$2 eq "buildroot"} { vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 # start and run simulation if { $coverage } { echo "wally-batch buildroot coverage" - vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt +cover=sbecf + vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G -o testbenchopt +cover=sbecf vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286 -fatal 7 -cover } else { - vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt + vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G -o testbenchopt vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286 -fatal 7 } @@ -76,7 +76,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { } elseif {$2 eq "buildroot-no-trace"} { vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 # start and run simulation - vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=1 -o testbenchopt + vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G -G NO_SPOOFING=1 -o testbenchopt vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7 #-- Run the Simulation diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 396fa1515..5c21d7ecd 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -196,8 +196,8 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign PreLSURWM = MemRWM; assign IHAdrM = IEUAdrExtM; assign LSUFunct3M = Funct3M; - assign LSUFunct7M = Funct7M; - assign LSUAtomicM = AtomicM; + assign LSUFunct7M = Funct7M; + assign LSUAtomicM = AtomicM; assign IHWriteDataM = WriteDataM; assign LoadAccessFaultM = LSULoadAccessFaultM; assign StoreAmoAccessFaultM = LSUStoreAmoAccessFaultM; diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv index 1cf719085..e1cc1795f 100644 --- a/testbench/common/loggers.sv +++ b/testbench/common/loggers.sv @@ -182,7 +182,7 @@ module loggers import cvw::*; #(parameter cvw_t P, (!dut.core.lsu.bus.dcache.dcache.vict.cacheLRU.AllValid) ? "M" : dut.core.lsu.bus.dcache.dcache.LineDirty ? "D" : "E"; AccessTypeString = dut.core.lsu.bus.dcache.FlushDCache ? "F" : - dut.core.lsu.bus.dcache.CacheAtomicM[1] ? "A" : + dut.core.lsu.LSUAtomicM[1] ? "A" : dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" : dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" : "NULL"; diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 1ba7f010d..746fde068 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -23,7 +23,7 @@ `define NUM_REGS 32 `define NUM_CSRS 4096 -`define STD_LOG 0 +`define STD_LOG 1 `define PRINT_PC_INSTR 0 `define PRINT_MOST 0 `define PRINT_ALL 0 @@ -502,7 +502,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); if(`STD_LOG) begin instrNameDecTB NameDecoder(rvvi.insn[0][0], instrWName); initial begin - LogFile = "logs/InstrTrace.log"; + LogFile = "logs/boottrace.log"; file = $fopen(LogFile, "w"); end end