diff --git a/fpga/constraints/constraints-ArtyA7.xdc b/fpga/constraints/constraints-ArtyA7.xdc index e4774280f..4dadf3987 100644 --- a/fpga/constraints/constraints-ArtyA7.xdc +++ b/fpga/constraints/constraints-ArtyA7.xdc @@ -136,8 +136,8 @@ set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports { set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCWP}] -set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCCS}] -set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCCS}] +set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCCS}] +set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCCS}] set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCIn}] set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCIn}] @@ -158,54 +158,54 @@ set_max_delay -datapath_only -from [get_pins xlnx_ddr3_c0/u_xlnx_ddr3_mig/u_memc # ddr3 -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[0] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[1] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[2] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[3] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[4] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[5] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[6] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[7] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[8] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[9] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[10] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[11] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[12] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[13] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[14] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[15] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[0] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[1] -set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[0] -set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[0] -set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[1] -set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[1] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[13] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[12] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[11] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[10] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[9] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[8] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[7] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[6] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[5] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[4] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[3] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[2] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[1] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[0] -set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[2] -set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[1] -set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[0] -set_property IOSTANDARD DIFF [get_ports ddr3_ck_p[0] -set_property IOSTANDARD DIFF [get_ports ddr3_ck_n[0] -set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n -set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n -set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n -set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n -set_property IOSTANDARD SSTL135 [get_ports ddr3_cke[0] -set_property IOSTANDARD SSTL135 [get_ports ddr3_odt[0] -set_property IOSTANDARD SSTL135 [get_ports ddr3_cs_n[0] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[0]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[1]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[2]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[3]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[4]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[5]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[6]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[7]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[8]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[9]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[10]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[11]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[12]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[13]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[14]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[15]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[0]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[1]] +set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[0]] +set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[0]] +set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[1]] +set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[1]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[13]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[12]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[11]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[10]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[9]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[8]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[7]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[6]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[5]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[4]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[3]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[2]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[1]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[0]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[2]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[1]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[0]] +set_property IOSTANDARD DIFF [get_ports ddr3_ck_p[0]] +set_property IOSTANDARD DIFF [get_ports ddr3_ck_n[0]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n] +set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n] +set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n] +set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n] +set_property IOSTANDARD SSTL135 [get_ports ddr3_cke[0]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_odt[0]] +set_property IOSTANDARD SSTL135 [get_ports ddr3_cs_n[0]] set_properity PACKAGE_PIN K5 [get_ports ddr3_dq[0]] diff --git a/src/uncore/spi_apb.sv b/src/uncore/spi_apb.sv index 7d562434e..eb4f95047 100644 --- a/src/uncore/spi_apb.sv +++ b/src/uncore/spi_apb.sv @@ -319,7 +319,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( else if ((~TransmitFIFOReadEmpty | ~TransmitShiftEmpty)) begin state <= ACTIVE_0; SPICLK <= ~SckMode[1]; - end + end else SPICLK <= SckMode[1]; end DELAY_0: begin CS_SCKCount <= CS_SCKCount + 9'b1; @@ -357,6 +357,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( end INTER_CS: begin InterCSCount <= InterCSCount + 9'b1; + SPICLK <= SckMode[1]; if (InterCSCount >= ({Delay1[7:0],1'b0})) state <= CS_INACTIVE; end INTER_XFR: begin @@ -369,6 +370,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( state <= ACTIVE_0; SPICLK <= ~SckMode[1]; end else if (~|ChipSelectMode[1:0]) state <= CS_INACTIVE; + else SPICLK <= SckMode[1]; end endcase /* verilator lint_off CASEINCOMPLETE */ @@ -382,7 +384,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( assign Active = (state == ACTIVE_0 | state == ACTIVE_1); assign SampleEdge = SckMode[0] ? (state == ACTIVE_1) : (state == ACTIVE_0); assign ZeroDelayHoldMode = ((ChipSelectMode == 2'b10) & (~|(Delay1[7:4]))); - assign TransmitInactive = ((state == INTER_CS) | (state == CS_INACTIVE) | (state == INTER_XFR) | (ReceiveShiftFullDelayPCLK & ZeroDelayHoldMode) | ((state == ACTIVE_1) & ((ChipSelectMode[1:0] == 2'b10) & ~|(Delay1[15:8]) & (~TransmitFIFOReadEmpty) & (FrameCount == 4'd8)))); + assign TransmitInactive = ((state == INTER_CS) | (state == CS_INACTIVE) | (state == INTER_XFR) | (ReceiveShiftFullDelayPCLK & ZeroDelayHoldMode) | ((state == ACTIVE_1) & ((ChipSelectMode[1:0] == 2'b10) & ~|(Delay1[15:8]) & (~TransmitFIFOReadEmpty) & (FrameCount == Format[4:1])))); assign Active0 = (state == ACTIVE_0); // Signal tracks which edge of sck to shift data @@ -392,9 +394,9 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( always_comb case(SckMode[1:0]) 2'b00: ShiftEdge = SPICLK & SCLKenable; - 2'b01: ShiftEdge = (SPICLK & |(FrameCount) & SCLKenable); // Probably wrong + 2'b01: ShiftEdge = (~SPICLK & (|(FrameCount) | (CS_SCKCount >= (({Delay0[7:0], 1'b0}) + ImplicitDelay1))) & SCLKenable & (FrameCount != Format[4:1]) & ~TransmitInactive); // Probably wrong 2'b10: ShiftEdge = ~SPICLK & SCLKenable; // Probably wrong - 2'b11: ShiftEdge = (~SPICLK & |(FrameCount) & SCLKenable); // Probably wrong + 2'b11: ShiftEdge = (SPICLK & (|(FrameCount) | (CS_SCKCount >= (({Delay0[7:0], 1'b0}) + ImplicitDelay1))) & SCLKenable & (FrameCount != Format[4:1]) & ~TransmitInactive); // Probably wrong default: ShiftEdge = SPICLK & SCLKenable; endcase diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-spi-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-spi-01.reference_output index ebc48ae2e..b006e3229 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-spi-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-spi-01.reference_output @@ -88,6 +88,8 @@ 0000000B +000000F3 + 00000079 00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-spi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-spi-01.S index 3d0abc6a0..68d3785e8 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-spi-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-spi-01.S @@ -178,6 +178,12 @@ test_cases: .4byte 0x0, 0x00000000, spi_data_wait # wait for transmission to end .4byte rx_data, 0x0000000B, read32_test # read rx_data +# Test phase polarity +.4byte sck_mode, 0x00000003, write32_test # set sck mode to 11 +.4byte tx_data, 0x000000F3, write32_test # place f3 into tx_data +.4byte 0x0, 0x00000000, spi_data_wait # wait for transmission to end +.4byte rx_data, 0x000000F3, read32_test # read rx_data + # Test chip select polarity .4byte sck_mode, 0x00000000, write32_test # reset sck polarity to active high @@ -658,4 +664,4 @@ SETUP_PLIC -.4byte 0x0, 0x0, terminate_test \ No newline at end of file +.4byte 0x0, 0x0, terminate_test diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-spi-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-spi-01.reference_output index 83376aab1..673395696 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-spi-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-spi-01.reference_output @@ -88,6 +88,8 @@ 00000000 0000000B 00000000 +000000F3 +00000000 00000079 00000000 00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-spi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-spi-01.S index 11aebe333..21b38f9b8 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-spi-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-spi-01.S @@ -180,6 +180,12 @@ test_cases: .8byte 0x0, 0x00000000, spi_data_wait # wait for transmission to end .8byte rx_data, 0x0000000B, read32_test # read rx_data +# Test phase polarity +.8byte sck_mode, 0x00000003, write32_test # set sck mode to 11 +.8byte tx_data, 0x000000F3, write32_test # place f3 into tx_data +.8byte 0x0, 0x00000000, spi_data_wait # wait for transmission to end +.8byte rx_data, 0x000000F3, read32_test # read rx_data + # Test chip select polarity .8byte sck_mode, 0x00000000, write32_test # reset sck polarity to active high @@ -660,4 +666,4 @@ SETUP_PLIC -.8byte 0x0, 0x0, terminate_test \ No newline at end of file +.8byte 0x0, 0x0, terminate_test