From d89d595cb4398de2e306c3002b7c69558af13edb Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Wed, 22 Jan 2025 04:34:53 -0800
Subject: [PATCH] Cleaned up tracer parameters

---
 testbench/common/wallyTracer.sv | 37 ++++++++++++++++-----------------
 1 file changed, 18 insertions(+), 19 deletions(-)

diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv
index 093b72de2..468e53d40 100644
--- a/testbench/common/wallyTracer.sv
+++ b/testbench/common/wallyTracer.sv
@@ -2,6 +2,8 @@
 // wallyTracer.sv
 //
 // A component of the Wally configurable RISC-V project.
+// Implements a RISC-V Verification Interface (RVVI)
+// to support functional coverage and lockstep simulation.
 // 
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //
@@ -20,19 +22,16 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 
-`define NUM_REGS 32
-`define NUM_CSRS 4096
-
 `define STD_LOG 0
 `define PRINT_PC_INSTR 0
 `define PRINT_MOST 0
 `define PRINT_ALL 0
 `define PRINT_CSRS 0
 
-
 module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
 
-  localparam NUMREGS = P.E_SUPPORTED ? 16 : 32;
+  localparam NUM_REGS = P.E_SUPPORTED ? 16 : 32;
+  localparam NUM_CSRS = 4096;
   
   // wally specific signals
   logic                  reset;
@@ -50,17 +49,17 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   logic                  TrapM, TrapW;
   logic                  HaltM, HaltW;
   logic [1:0]            PrivilegeModeW;
-  logic [P.XLEN-1:0]     rf[NUMREGS];
-  logic [NUMREGS-1:0]    rf_wb;
+  logic [P.XLEN-1:0]     rf[NUM_REGS];
+  logic [NUM_REGS-1:0]   rf_wb;
   logic [4:0]            rf_a3;
   logic                  rf_we3;
   logic [P.FLEN-1:0]     frf[32];
-  logic [`NUM_REGS-1:0]  frf_wb;
+  logic [NUM_REGS-1:0]   frf_wb;
   logic [4:0]            frf_a4;
   logic                  frf_we4;
   logic [P.XLEN-1:0]     CSRArray [4095:0];
   logic [P.XLEN-1:0]     CSRArrayOld [4095:0];
-  logic [`NUM_CSRS-1:0]  CSR_W;
+  logic [NUM_CSRS-1:0]  CSR_W;
   logic                  CSRWriteM, CSRWriteW;
   logic [11:0]           CSRAdrM, CSRAdrW;
   logic                  wfiM;
@@ -314,7 +313,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
 
   genvar index;
   assign rf[0] = 0;
-  for(index = 1; index < NUMREGS; index += 1) 
+  for(index = 1; index < NUM_REGS; index += 1) 
   assign rf[index] = testbench.dut.core.ieu.dp.regf.rf[index];
 
   assign rf_a3  = testbench.dut.core.ieu.dp.regf.a3;
@@ -329,12 +328,12 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   if (P.F_SUPPORTED) begin
     assign frf_a4  = testbench.dut.core.fpu.fpu.fregfile.a4;
     assign frf_we4 = testbench.dut.core.fpu.fpu.fregfile.we4;
-    for(index = 0; index < NUMREGS; index += 1) 
+    for(index = 0; index < NUM_REGS; index += 1) 
       assign frf[index] = testbench.dut.core.fpu.fpu.fregfile.rf[index];
   end else begin
     assign frf_a4  = '0;
     assign frf_we4 = 0;
-    for(index = 0; index < NUMREGS; index += 1) 
+    for(index = 0; index < NUM_REGS; index += 1) 
       assign frf[index] = '0;
   end
   
@@ -420,7 +419,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
                                ~FlushE ? PCD :
                                ~FlushD ? PCF : PCNextF;
 
-  for(index = 0; index < `NUM_REGS; index += 1) begin
+  for(index = 0; index < NUM_REGS; index += 1) begin
     assign rvvi.x_wdata[0][0][index] = rf[index];
     assign rvvi.x_wb[0][0][index]    = rf_wb[index];
     assign rvvi.f_wdata[0][0][index] = frf[index];
@@ -744,18 +743,18 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
 	if(valid) begin
       if(`STD_LOG) begin
         $fwrite(file, "%016x, %08x, %s\t\t", rvvi.pc_rdata[0][0], rvvi.insn[0][0], instrWName);
-        for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
+        for(index2 = 0; index2 < NUM_REGS; index2 += 1) begin
           if(rvvi.x_wb[0][0][index2]) begin
             $fwrite(file, "rf[%02d] = %016x ", index2, rvvi.x_wdata[0][0][index2]);
           end
         end
       end
-      for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
+      for(index2 = 0; index2 < NUM_REGS; index2 += 1) begin
         if(rvvi.f_wb[0][0][index2]) begin
           $fwrite(file, "frf[%02d] = %016x ", index2, rvvi.f_wdata[0][0][index2]);
         end
       end
-      for(index2 = 0; index2 < `NUM_CSRS; index2 += 1) begin
+      for(index2 = 0; index2 < NUM_CSRS; index2 += 1) begin
         if(rvvi.csr_wb[0][0][index2]) begin
           $fwrite(file, "csr[%03x] = %016x ", index2, rvvi.csr[0][0][index2]);
         end
@@ -769,15 +768,15 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
       else if(`PRINT_ALL) begin
         $display("order = %08d, PC = %08x, insn = %08x, trap = %1d, halt = %1d, intr = %1d, mode = %1x, ixl = %1x, pc_wdata = %08x", 
                  rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0], rvvi.trap[0][0], rvvi.halt[0][0], rvvi.intr[0][0], rvvi.mode[0][0], rvvi.ixl[0][0], rvvi.pc_wdata[0][0]);
-        for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
+        for(index2 = 0; index2 < NUM_REGS; index2 += 1) begin
           $display("x%02d = %08x", index2, rvvi.x_wdata[0][0][index2]);
         end
-        for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
+        for(index2 = 0; index2 < NUM_REGS; index2 += 1) begin
           $display("f%02d = %08x", index2, rvvi.f_wdata[0][0][index2]);
         end
       end
       if (`PRINT_CSRS) begin
-        for(index2 = 0; index2 < `NUM_CSRS; index2 += 1) begin
+        for(index2 = 0; index2 < NUM_CSRS; index2 += 1) begin
           if(CSR_W[index2]) begin
             $display("%t: CSR %03x = %x", $time(), index2, CSRArray[index2]);
           end