From d81af3bca885b27f6b360599f0db28c695ae37c6 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 29 Sep 2022 11:24:15 -0500 Subject: [PATCH] Fixed HTRANS not changing after accepting HREADY. This exposed a bug in uncore. --- pipelined/src/ebu/buscachefsm.sv | 1 - pipelined/src/ebu/busfsm.sv | 3 +-- pipelined/src/uncore/uncore.sv | 2 +- 3 files changed, 2 insertions(+), 4 deletions(-) diff --git a/pipelined/src/ebu/buscachefsm.sv b/pipelined/src/ebu/buscachefsm.sv index 6d4e3e03b..5fc91d6d4 100644 --- a/pipelined/src/ebu/buscachefsm.sv +++ b/pipelined/src/ebu/buscachefsm.sv @@ -140,7 +140,6 @@ module buscachefsm #(parameter integer WordCountThreshold, // AHB bus interface assign HTRANS = (CurrState == ADR_PHASE & HREADY & (|BusRW | |CacheBusRW)) | - (CurrState == DATA_PHASE & ~HREADY) | // *** this is wrong. (CacheAccess & FinalWordCount & |CacheBusRW & HREADY) ? AHB_NONSEQ : // if we have a pipelined request (CacheAccess & |WordCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE; diff --git a/pipelined/src/ebu/busfsm.sv b/pipelined/src/ebu/busfsm.sv index 6d80ca3b4..336c3b4e2 100644 --- a/pipelined/src/ebu/busfsm.sv +++ b/pipelined/src/ebu/busfsm.sv @@ -76,8 +76,7 @@ module busfsm assign BusCommitted = CurrState != ADR_PHASE; - assign HTRANS = (CurrState == ADR_PHASE & HREADY & |BusRW) | - (CurrState == DATA_PHASE & ~HREADY) ? AHB_NONSEQ : AHB_IDLE; + assign HTRANS = (CurrState == ADR_PHASE & HREADY & |BusRW) ? AHB_NONSEQ : AHB_IDLE; assign HWRITE = BusRW[0]; assign CaptureEn = CurrState == DATA_PHASE; diff --git a/pipelined/src/uncore/uncore.sv b/pipelined/src/uncore/uncore.sv index eeaec9fae..d782ce7a4 100644 --- a/pipelined/src/uncore/uncore.sv +++ b/pipelined/src/uncore/uncore.sv @@ -203,6 +203,6 @@ module uncore ( // However on reset None must be seleted. flopenr #(10) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions[10:1], {HSELDTIMD, HSELIROMD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD}); flopenl #(1) hseldelayreg2(HCLK, ~HRESETn, HREADY, HSELRegions[0], 1'b1, HSELNoneD); - flopr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HSELBRIDGE, HSELBRIDGED); + flopenr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HREADY, HSELBRIDGE, HSELBRIDGED); endmodule