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Swap in branch predictor simulator handling compressed instruction offsets

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This commit is contained in:
David Harris 2023-11-21 16:42:41 -08:00
parent 93a0db1fca
commit d8186b9f58
2 changed files with 4 additions and 0 deletions
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3
.gitmodules vendored
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@ -26,3 +26,6 @@
[submodule "addins/riscv-arch-test"] [submodule "addins/riscv-arch-test"]
path = addins/riscv-arch-test path = addins/riscv-arch-test
url = https://github.com/riscv-non-isa/riscv-arch-test url = https://github.com/riscv-non-isa/riscv-arch-test
[submodule "addins/branch-predictor-simulator"]
path = addins/branch-predictor-simulator
url = https://github.com/ross144/branch-predictor-simulator

1
addins/branch-predictor-simulator Submodule

@ -0,0 +1 @@
Subproject commit 3e424e902f2088d0c9f482f3900ab780affb6350