From 7a196d3fa7f7851a632c041fadbea413159ab336 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 31 Jul 2023 14:12:53 -0500 Subject: [PATCH 01/24] Cache cleanup. --- src/cache/cache.sv | 1 - src/cache/cachefsm.sv | 13 +++++-------- src/ifu/ifu.sv | 2 +- src/lsu/lsu.sv | 2 +- 4 files changed, 7 insertions(+), 11 deletions(-) diff --git a/src/cache/cache.sv b/src/cache/cache.sv index d4d03a302..3910333ed 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -33,7 +33,6 @@ module cache import cvw::*; #(parameter cvw_t P, input logic reset, input logic Stall, // Stall the cache, preventing new accesses. In-flight access finished but does not return to READY input logic FlushStage, // Pipeline flush of second stage (prevent writes and bus operations) - input logic IgnoreRequestTLB, // // cpu side input logic [1:0] CacheRW, // [1] Read, [0] Write input logic [1:0] CacheAtomic, // Atomic operation diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 58aa9b477..6f7ff1500 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -67,7 +67,6 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( ); logic resetDelay; - logic StoreAMO; logic AnyUpdateHit, AnyHit; logic AnyMiss; logic FlushFlag; @@ -84,10 +83,8 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( statetype CurrState, NextState; - assign StoreAMO = CacheRW[0]; // AMO operations assert CacheRW[0] - - assign AnyMiss = (StoreAMO | CacheRW[1]) & ~CacheHit & ~InvalidateCache; // exclusion-tag: cache AnyMiss - assign AnyUpdateHit = (StoreAMO) & CacheHit; // exclusion-tag: icache storeAMO1 + assign AnyMiss = (CacheRW[0] | CacheRW[1]) & ~CacheHit & ~InvalidateCache; // exclusion-tag: cache AnyMiss + assign AnyUpdateHit = (CacheRW[0]) & CacheHit; // exclusion-tag: icache storeAMO1 assign AnyHit = AnyUpdateHit | (CacheRW[1] & CacheHit); // exclusion-tag: icache AnyUpdateHit assign FlushFlag = FlushAdrFlag & FlushWayFlag; @@ -148,8 +145,8 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( (CurrState == STATE_WRITE_LINE) & ~FlushStage; // exclusion-tag-start: icache flushdirtycontrols assign SetDirty = (CurrState == STATE_READY & AnyUpdateHit) | // exclusion-tag: icache SetDirty - (CurrState == STATE_WRITE_LINE & (StoreAMO)); - assign ClearDirty = (CurrState == STATE_WRITE_LINE & ~(StoreAMO)) | // exclusion-tag: icache ClearDirty + (CurrState == STATE_WRITE_LINE & (CacheRW[0])); + assign ClearDirty = (CurrState == STATE_WRITE_LINE & ~(CacheRW[0])) | // exclusion-tag: icache ClearDirty (CurrState == STATE_FLUSH & LineDirty); // This is wrong in a multicore snoop cache protocal. Dirty must be cleared concurrently and atomically with writeback. For single core cannot clear after writeback on bus ack and change flushadr. Clears the wrong set. // Flush and eviction controls assign SelWriteback = (CurrState == STATE_WRITEBACK & ~CacheBusAck) | @@ -175,7 +172,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( (CurrState == STATE_WRITEBACK & ~CacheBusAck) | (CurrState == STATE_FLUSH_WRITEBACK & ~CacheBusAck); - assign SelAdr = (CurrState == STATE_READY & (StoreAMO | AnyMiss)) | // exclusion-tag: icache SelAdrCauses // changes if store delay hazard removed + assign SelAdr = (CurrState == STATE_READY & (CacheRW[0] | AnyMiss)) | // exclusion-tag: icache SelAdrCauses // changes if store delay hazard removed (CurrState == STATE_FETCH) | (CurrState == STATE_WRITEBACK) | (CurrState == STATE_WRITE_LINE) | diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index db588441f..95c75c3c7 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -236,7 +236,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.ICACHE_LINELENINBITS), .NUMLINES(P.ICACHE_WAYSIZEINBYTES*8/P.ICACHE_LINELENINBITS), .NUMWAYS(P.ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .READ_ONLY_CACHE(1)) - icache(.clk, .reset, .FlushStage(FlushD), .IgnoreRequestTLB(1'b0), .Stall(GatedStallD), + icache(.clk, .reset, .FlushStage(FlushD), .Stall(GatedStallD), .FetchBuffer, .CacheBusAck(ICacheBusAck), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), .CacheBusRW, diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 3584a05c8..a80fb055e 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -268,7 +268,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( // *** prefetch can just act as a read operation cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMLINES(P.DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(P.LLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache( - .clk, .reset, .Stall(GatedStallW), .SelBusBeat, .FlushStage(FlushW | IgnoreRequestTLB), .IgnoreRequestTLB, .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM), + .clk, .reset, .Stall(GatedStallW), .SelBusBeat, .FlushStage(FlushW | IgnoreRequestTLB), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM), .FlushCache(FlushDCache), .NextSet(IEUAdrE[11:0]), .PAdr(PAdrM), .ByteMask(ByteMaskM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]), .CacheWriteData(LSUWriteDataM), .SelHPTW, From 06efd2cdde2aeb883c64d25324bccf9f878f47b0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 31 Jul 2023 14:13:09 -0500 Subject: [PATCH 02/24] Pushed performance of arty a7 to 23Mhz. --- fpga/constraints/marked_debug.txt | 134 ++---------------------------- fpga/generator/wally.tcl | 2 +- fpga/generator/xlnx_mmcm.tcl | 2 +- linux/devicetree/wally-artya7.dts | 12 +-- 4 files changed, 13 insertions(+), 137 deletions(-) diff --git a/fpga/constraints/marked_debug.txt b/fpga/constraints/marked_debug.txt index 3973fc451..9b7927e10 100644 --- a/fpga/constraints/marked_debug.txt +++ b/fpga/constraints/marked_debug.txt @@ -1,131 +1,7 @@ -lsu/lsu.sv: logic IEUAdrM -lsu/lsu.sv: logic WriteDataM -lsu/lsu.sv: logic LSUHADDR -lsu/lsu.sv: logic HRDATA -lsu/lsu.sv: logic LSUHWDATA -lsu/lsu.sv: logic LSUHREADY -lsu/lsu.sv: logic LSUHWRITE -lsu/lsu.sv: logic LSUHSIZE -lsu/lsu.sv: logic LSUHBURST -lsu/lsu.sv: logic LSUHTRANS -lsu/lsu.sv: logic LSUHWSTRB -lsu/lsu.sv: logic IHAdrM -ieu/regfile.sv: logic rf -ieu/datapath.sv: logic RegWriteW -hazard/hazard.sv: logic BPPredWrongE -hazard/hazard.sv: logic LoadStallD -hazard/hazard.sv: logic FCvtIntStallD -hazard/hazard.sv: logic DivBusyE -hazard/hazard.sv: logic EcallFaultM -hazard/hazard.sv: logic WFIStallM -hazard/hazard.sv: logic StallF -hazard/hazard.sv: logic FlushD -cache/cachefsm.sv: statetype CurrState -wally/wallypipelinedcore.sv: logic TrapM -wally/wallypipelinedcore.sv: logic SrcAM -wally/wallypipelinedcore.sv: logic InstrM wally/wallypipelinedcore.sv: logic PCM -wally/wallypipelinedcore.sv: logic MemRWM +wally/wallypipelinedcore.sv: logic TrapM wally/wallypipelinedcore.sv: logic InstrValidM -wally/wallypipelinedcore.sv: logic WriteDataM -wally/wallypipelinedcore.sv: logic IEUAdrM -wally/wallypipelinedcore.sv: logic HRDATA -ifu/spill.sv: statetype CurrState -ifu/ifu.sv: logic IFUStallF -ifu/ifu.sv: logic IFUHADDR -ifu/ifu.sv: logic HRDATA -ifu/ifu.sv: logic IFUHREADY -ifu/ifu.sv: logic IFUHWRITE -ifu/ifu.sv: logic IFUHSIZE -ifu/ifu.sv: logic IFUHBURST -ifu/ifu.sv: logic IFUHTRANS -ifu/ifu.sv: logic PCF -ifu/ifu.sv: logic PCNextF -ifu/ifu.sv: logic PCPF -ifu/ifu.sv: logic PostSpillInstrRawF -mmu/hptw.sv: logic ITLBWriteF -mmu/hptw.sv: statetype WalkerState -privileged/csrs.sv: logic CSRSReadValM -privileged/csrs.sv: logic SEPC_REGW -privileged/csrs.sv: logic MIP_REGW -privileged/csrs.sv: logic SSCRATCH_REGW -privileged/csrs.sv: logic SCAUSE_REGW -privileged/csr.sv: logic CSRReadValM -privileged/csr.sv: logic CSRSrcM -privileged/csr.sv: logic CSRWriteValM -privileged/csr.sv: logic MSTATUS_REGW -privileged/trap.sv: logic InstrMisalignedFaultM -privileged/trap.sv: logic BreakpointFaultM -privileged/trap.sv: logic LoadAccessFaultM -privileged/trap.sv: logic LoadPageFaultM -privileged/trap.sv: logic mretM -privileged/trap.sv: logic MIP_REGW -privileged/trap.sv: logic PendingIntsM -privileged/privileged.sv: logic CSRReadM -privileged/privileged.sv: logic InterruptM -privileged/csrc.sv: logic HPMCOUNTER_REGW -privileged/csri.sv: logic MExtInt -privileged/csri.sv: logic MIP_REGW_writeabl -privileged/csrm.sv: logic MIP_REGW -privileged/csrm.sv: logic MEPC_REGW -privileged/csrm.sv: logic MEDELEG_REGW -privileged/csrm.sv: logic MIDELEG_REGW -privileged/csrm.sv: logic MSCRATCH_REGW -privileged/csrm.sv: logic MCAUSE_REGW -uncore/uart_apb.sv: logic SIN -uncore/uart_apb.sv: logic SOUT -uncore/uart_apb.sv: logic OUT1b -uncore/uartPC16550D.sv: logic RBR -uncore/uartPC16550D.sv: logic FCR -uncore/uartPC16550D.sv: logic IER -uncore/uartPC16550D.sv: logic MCR -uncore/uartPC16550D.sv: logic baudpulse -uncore/uartPC16550D.sv: statetype rxstate -uncore/uartPC16550D.sv: logic rxfifo -uncore/uartPC16550D.sv: logic txfifo -uncore/uartPC16550D.sv: logic rxfifohead -uncore/uartPC16550D.sv: logic rxfifoentries -uncore/uartPC16550D.sv: logic RXBR -uncore/uartPC16550D.sv: logic rxtimeoutcnt -uncore/uartPC16550D.sv: logic rxparityerr -uncore/uartPC16550D.sv: logic rxdataready -uncore/uartPC16550D.sv: logic rxfifoempty -uncore/uartPC16550D.sv: logic rxdata -uncore/uartPC16550D.sv: logic RXerrbit -uncore/uartPC16550D.sv: logic rxfullbitunwrapped -uncore/uartPC16550D.sv: logic txdata -uncore/uartPC16550D.sv: logic txnextbit -uncore/uartPC16550D.sv: logic txfifoempty -uncore/uartPC16550D.sv: logic fifoenabled -uncore/uartPC16550D.sv: logic RXerr -uncore/uartPC16550D.sv: logic THRE -uncore/uartPC16550D.sv: logic rxdataavailintr -uncore/uartPC16550D.sv: logic intrID -uncore/uncore.sv: logic HSELEXTSDCD -uncore/plic_apb.sv: logic MExtInt -uncore/plic_apb.sv: logic Din -uncore/plic_apb.sv: logic requests -uncore/plic_apb.sv: logic intPriority -uncore/plic_apb.sv: logic intInProgress -uncore/plic_apb.sv: logic intThreshold -uncore/plic_apb.sv: logic intEn -uncore/plic_apb.sv: logic intClaim -uncore/plic_apb.sv: logic irqMatrix -uncore/plic_apb.sv: logic priorities_with_irqs -uncore/plic_apb.sv: logic max_priority_with_irqs -uncore/plic_apb.sv: logic irqs_at_max_priority -uncore/plic_apb.sv: logic threshMask -uncore/clint_apb.sv: logic MTIME -uncore/clint_apb.sv: logic MTIMECMP -ebu/ebu.sv: logic HCLK -ebu/ebu.sv: logic HREADY -ebu/ebu.sv: logic HRESP -ebu/ebu.sv: logic HADDR -ebu/ebu.sv: logic HWRITE -ebu/ebu.sv: logic HSIZE -ebu/ebu.sv: logic HBURST -ebu/ebu.sv: logic HPROT -ebu/ebu.sv: logic HTRANS -ebu/ebu.sv: logic HMASTLOC -ebu/buscachefsm.sv: busstatetype CurrState -ebu/busfsm.sv: busstatetype CurrState +wally/wallypipelinedcore.sv: logic InstrM +lsu/lsu.sv: logic LSUHADDR +lsu/lsu.sv: logic LSUHREADY +lsu/lsu.sv: logic LSUHWDATA diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index d4e3dc2df..a3c7eec47 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -69,7 +69,7 @@ exec rm -rf reports/* report_compile_order -constraints > reports/compile_order.rpt # this is elaboration not synthesis. -synth_design -rtl -name rtl_1 +synth_design -rtl -name rtl_1 -flatten_hierarchy full report_clocks -file reports/clocks.rpt diff --git a/fpga/generator/xlnx_mmcm.tcl b/fpga/generator/xlnx_mmcm.tcl index 2f003e7a5..a8a2fe568 100644 --- a/fpga/generator/xlnx_mmcm.tcl +++ b/fpga/generator/xlnx_mmcm.tcl @@ -15,7 +15,7 @@ set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \ CONFIG.CLKOUT4_USED {false} \ CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \ CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \ - CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {23} \ CONFIG.CLKIN1_JITTER_PS {10.0} \ ] [get_ips $ipName] diff --git a/linux/devicetree/wally-artya7.dts b/linux/devicetree/wally-artya7.dts index ed1c9c85d..57b9599e5 100644 --- a/linux/devicetree/wally-artya7.dts +++ b/linux/devicetree/wally-artya7.dts @@ -21,8 +21,8 @@ cpus { #address-cells = <0x01>; #size-cells = <0x00>; - clock-frequency = <0x1312D00>; - timebase-frequency = <0x1312D00>; + clock-frequency = <0x15EF3C0>; + timebase-frequency = <0x15EF3C0>; cpu@0 { phandle = <0x01>; @@ -51,7 +51,7 @@ uart@10000000 { interrupts = <0x0a>; interrupt-parent = <0x03>; - clock-frequency = <0x1312D00>; + clock-frequency = <0x15EF3C0>; reg = <0x00 0x10000000 0x00 0x100>; compatible = "ns16550a"; }; @@ -74,11 +74,11 @@ fifo-depth = <256>; bus-width = <4>; interrupt-parent = <0x03>; - clock = <0x1312D00>; - max-frequency = <0x1312D00>; + clock = <0x15EF3C0>; + max-frequency = <0x15EF3C0>; cap-sd-highspeed; cap-mmc-highspeed; - sdio; + no-sdio; }; clint@2000000 { From c4ae856f9215b4ceb3bf21b2d329f5f16b1b1d48 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 1 Aug 2023 14:39:33 -0500 Subject: [PATCH 03/24] Clean up vcu118 synth scripts. --- fpga/constraints/constraints-vcu118.xdc | 12 +- fpga/constraints/debug4.xdc | 175 ------------------------ fpga/constraints/marked_debug.txt | 134 +++++++++++++++++- fpga/generator/wally.tcl | 3 +- fpga/generator/xlnx_ddr4-vcu118.tcl | 2 +- 5 files changed, 138 insertions(+), 188 deletions(-) diff --git a/fpga/constraints/constraints-vcu118.xdc b/fpga/constraints/constraints-vcu118.xdc index 3bd9db8b3..7b70950a5 100644 --- a/fpga/constraints/constraints-vcu118.xdc +++ b/fpga/constraints/constraints-vcu118.xdc @@ -16,7 +16,7 @@ set_property IOSTANDARD LVCMOS18 [get_ports {GPI[1]}] set_property IOSTANDARD LVCMOS18 [get_ports {GPI[0]}] set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {GPI[*]}] set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports {GPI[*]}] -set_max_delay -from [get_ports {GPI[*]}] 10.000 +set_max_delay -from [get_ports {GPI[*]}] 20.000 ##### GPO #### set_property PACKAGE_PIN AT32 [get_ports {GPO[0]}] @@ -29,7 +29,7 @@ set_property IOSTANDARD LVCMOS12 [get_ports {GPO[3]}] set_property IOSTANDARD LVCMOS12 [get_ports {GPO[2]}] set_property IOSTANDARD LVCMOS12 [get_ports {GPO[1]}] set_property IOSTANDARD LVCMOS12 [get_ports {GPO[0]}] -set_max_delay -to [get_ports {GPO[*]}] 10.000 +set_max_delay -to [get_ports {GPO[*]}] 20.000 set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {GPO[*]}] set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {GPO[*]}] @@ -39,8 +39,8 @@ set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_por set_property PACKAGE_PIN L31 [get_ports UARTSin] #set_property PACKAGE_PIN BB21 [get_ports UARTSout] set_property PACKAGE_PIN P29 [get_ports UARTSout] -set_max_delay -from [get_ports UARTSin] 10.000 -set_max_delay -to [get_ports UARTSout] 10.000 +set_max_delay -from [get_ports UARTSin] 20.000 +set_max_delay -to [get_ports UARTSout] 20.000 set_property IOSTANDARD LVCMOS12 [get_ports UARTSin] set_property IOSTANDARD LVCMOS12 [get_ports UARTSout] set_property DRIVE 6 [get_ports UARTSout] @@ -57,7 +57,7 @@ set_input_delay -clock [get_clocks mmcm_clkout0] -min -add_delay 0.000 [get_port set_input_delay -clock [get_clocks mmcm_clkout0] -max -add_delay 0.000 [get_ports reset] set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports reset] set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports reset] -set_max_delay -from [get_ports reset] 15.000 +set_max_delay -from [get_ports reset] 20.000 set_false_path -from [get_ports reset] set_property PACKAGE_PIN L19 [get_ports {reset}] set_property IOSTANDARD LVCMOS12 [get_ports {reset}] @@ -253,7 +253,7 @@ set_property PACKAGE_PIN G22 [get_ports {c0_ddr4_dm_dbi_n[7]}] -set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000 +set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 20.000 set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n] diff --git a/fpga/constraints/debug4.xdc b/fpga/constraints/debug4.xdc index 170b38346..78dc6caaa 100644 --- a/fpga/constraints/debug4.xdc +++ b/fpga/constraints/debug4.xdc @@ -717,178 +717,3 @@ set_property port_width 64 [get_debug_ports u_ila_0/probe138] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe138] connect_debug_port u_ila_0/probe138 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe139] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe139] -connect_debug_port u_ila_0/probe139 [get_nets [list {m_axi_awid[0]} {m_axi_awid[1]} {m_axi_awid[2]} {m_axi_awid[3]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe140] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe140] -connect_debug_port u_ila_0/probe140 [get_nets [list {m_axi_awlen[0]} {m_axi_awlen[1]} {m_axi_awlen[2]} {m_axi_awlen[3]} {m_axi_awlen[4]} {m_axi_awlen[5]} {m_axi_awlen[6]} {m_axi_awlen[7]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe141] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe141] -connect_debug_port u_ila_0/probe141 [get_nets [list {m_axi_awsize[0]} {m_axi_awsize[1]} {m_axi_awsize[2]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe142] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe142] -connect_debug_port u_ila_0/probe142 [get_nets [list {m_axi_awburst[0]} {m_axi_awburst[1]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe143] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe143] -connect_debug_port u_ila_0/probe143 [get_nets [list {m_axi_awcache[0]} {m_axi_awcache[1]} {m_axi_awcache[2]} {m_axi_awcache[3]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 31 [get_debug_ports u_ila_0/probe144] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe144] -connect_debug_port u_ila_0/probe144 [get_nets [list {m_axi_awaddr[0]} {m_axi_awaddr[1]} {m_axi_awaddr[2]} {m_axi_awaddr[3]} {m_axi_awaddr[4]} {m_axi_awaddr[5]} {m_axi_awaddr[6]} {m_axi_awaddr[7]} {m_axi_awaddr[8]} {m_axi_awaddr[9]} {m_axi_awaddr[10]} {m_axi_awaddr[11]} {m_axi_awaddr[12]} {m_axi_awaddr[13]} {m_axi_awaddr[14]} {m_axi_awaddr[15]} {m_axi_awaddr[16]} {m_axi_awaddr[17]} {m_axi_awaddr[18]} {m_axi_awaddr[19]} {m_axi_awaddr[20]} {m_axi_awaddr[21]} {m_axi_awaddr[22]} {m_axi_awaddr[23]} {m_axi_awaddr[24]} {m_axi_awaddr[25]} {m_axi_awaddr[26]} {m_axi_awaddr[27]} {m_axi_awaddr[28]} {m_axi_awaddr[29]} {m_axi_awaddr[30]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe145] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe145] -connect_debug_port u_ila_0/probe145 [get_nets [list {m_axi_awprot[0]} {m_axi_awprot[1]} {m_axi_awprot[2]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe146] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe146] -connect_debug_port u_ila_0/probe146 [get_nets [list {m_axi_awvalid}]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe147] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe147] -connect_debug_port u_ila_0/probe147 [get_nets [list {m_axi_awready}]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe148] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe148] -connect_debug_port u_ila_0/probe148 [get_nets [list {m_axi_awlock}]] - -create_debug_port u_ila_0 probe -set_property port_width 64 [get_debug_ports u_ila_0/probe149] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe149] -connect_debug_port u_ila_0/probe149 [get_nets [list {m_axi_wdata[0]} {m_axi_wdata[1]} {m_axi_wdata[2]} {m_axi_wdata[3]} {m_axi_wdata[4]} {m_axi_wdata[5]} {m_axi_wdata[6]} {m_axi_wdata[7]} {m_axi_wdata[8]} {m_axi_wdata[9]} {m_axi_wdata[10]} {m_axi_wdata[11]} {m_axi_wdata[12]} {m_axi_wdata[13]} {m_axi_wdata[14]} {m_axi_wdata[15]} {m_axi_wdata[16]} {m_axi_wdata[17]} {m_axi_wdata[18]} {m_axi_wdata[19]} {m_axi_wdata[20]} {m_axi_wdata[21]} {m_axi_wdata[22]} {m_axi_wdata[23]} {m_axi_wdata[24]} {m_axi_wdata[25]} {m_axi_wdata[26]} {m_axi_wdata[27]} {m_axi_wdata[28]} {m_axi_wdata[29]} {m_axi_wdata[30]} {m_axi_wdata[31]} {m_axi_wdata[32]} {m_axi_wdata[33]} {m_axi_wdata[34]} {m_axi_wdata[35]} {m_axi_wdata[36]} {m_axi_wdata[37]} {m_axi_wdata[38]} {m_axi_wdata[39]} {m_axi_wdata[40]} {m_axi_wdata[41]} {m_axi_wdata[42]} {m_axi_wdata[43]} {m_axi_wdata[44]} {m_axi_wdata[45]} {m_axi_wdata[46]} {m_axi_wdata[47]} {m_axi_wdata[48]} {m_axi_wdata[49]} {m_axi_wdata[50]} {m_axi_wdata[51]} {m_axi_wdata[52]} {m_axi_wdata[53]} {m_axi_wdata[54]} {m_axi_wdata[55]} {m_axi_wdata[56]} {m_axi_wdata[57]} {m_axi_wdata[58]} {m_axi_wdata[59]} {m_axi_wdata[60]} {m_axi_wdata[61]} {m_axi_wdata[62]} {m_axi_wdata[63]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe150] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe150] -connect_debug_port u_ila_0/probe150 [get_nets [list {m_axi_wstrb[0]} {m_axi_wstrb[1]} {m_axi_wstrb[2]} {m_axi_wstrb[3]} {m_axi_wstrb[4]} {m_axi_wstrb[5]} {m_axi_wstrb[6]} {m_axi_wstrb[7]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe151] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe151] -connect_debug_port u_ila_0/probe151 [get_nets [list {m_axi_wlast}]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe152] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe152] -connect_debug_port u_ila_0/probe152 [get_nets [list {m_axi_wvalid}]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe153] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe153] -connect_debug_port u_ila_0/probe153 [get_nets [list {m_axi_wready}]] - -create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe154] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe154] -connect_debug_port u_ila_0/probe154 [get_nets [list {m_axi_bid[0]} {m_axi_bid[1]} {m_axi_bid[2]} {m_axi_bid[3]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe155] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe155] -connect_debug_port u_ila_0/probe155 [get_nets [list {m_axi_bresp[0]} {m_axi_bresp[1]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe156] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe156] -connect_debug_port u_ila_0/probe156 [get_nets [list {m_axi_bvalid}]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe157] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe157] -connect_debug_port u_ila_0/probe157 [get_nets [list {m_axi_bready}]] - -create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe158] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe158] -connect_debug_port u_ila_0/probe158 [get_nets [list {m_axi_arid[0]} {m_axi_arid[1]} {m_axi_arid[2]} {m_axi_arid[3]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe159] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe159] -connect_debug_port u_ila_0/probe159 [get_nets [list {m_axi_arlen[0]} {m_axi_arlen[1]} {m_axi_arlen[2]} {m_axi_arlen[3]} {m_axi_arlen[4]} {m_axi_arlen[5]} {m_axi_arlen[6]} {m_axi_arlen[7]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe160] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe160] -connect_debug_port u_ila_0/probe160 [get_nets [list {m_axi_arsize[0]} {m_axi_arsize[1]} {m_axi_arsize[2]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe161] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe161] -connect_debug_port u_ila_0/probe161 [get_nets [list {m_axi_arburst[0]} {m_axi_arburst[1]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe162] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe162] -connect_debug_port u_ila_0/probe162 [get_nets [list {m_axi_arprot[0]} {m_axi_arprot[1]} {m_axi_arprot[2]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe163] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe163] -connect_debug_port u_ila_0/probe163 [get_nets [list {m_axi_arcache[0]} {m_axi_arcache[1]} {m_axi_arcache[2]} {m_axi_arcache[3]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe164] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe164] -connect_debug_port u_ila_0/probe164 [get_nets [list {m_axi_arvalid}]] - -create_debug_port u_ila_0 probe -set_property port_width 31 [get_debug_ports u_ila_0/probe165] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe165] -connect_debug_port u_ila_0/probe165 [get_nets [list {m_axi_araddr[0]} {m_axi_araddr[1]} {m_axi_araddr[2]} {m_axi_araddr[3]} {m_axi_araddr[4]} {m_axi_araddr[5]} {m_axi_araddr[6]} {m_axi_araddr[7]} {m_axi_araddr[8]} {m_axi_araddr[9]} {m_axi_araddr[10]} {m_axi_araddr[11]} {m_axi_araddr[12]} {m_axi_araddr[13]} {m_axi_araddr[14]} {m_axi_araddr[15]} {m_axi_araddr[16]} {m_axi_araddr[17]} {m_axi_araddr[18]} {m_axi_araddr[19]} {m_axi_araddr[20]} {m_axi_araddr[21]} {m_axi_araddr[22]} {m_axi_araddr[23]} {m_axi_araddr[24]} {m_axi_araddr[25]} {m_axi_araddr[26]} {m_axi_araddr[27]} {m_axi_araddr[28]} {m_axi_araddr[29]} {m_axi_araddr[30]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe166] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe166] -connect_debug_port u_ila_0/probe166 [get_nets [list {m_axi_arlock}]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe167] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe167] -connect_debug_port u_ila_0/probe167 [get_nets [list {m_axi_arready}]] - -create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe168] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe168] -connect_debug_port u_ila_0/probe168 [get_nets [list {m_axi_rid[0]} {m_axi_rid[1]} {m_axi_rid[2]} {m_axi_rid[3]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 64 [get_debug_ports u_ila_0/probe169] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe169] -connect_debug_port u_ila_0/probe169 [get_nets [list {m_axi_rdata[0]} {m_axi_rdata[1]} {m_axi_rdata[2]} {m_axi_rdata[3]} {m_axi_rdata[4]} {m_axi_rdata[5]} {m_axi_rdata[6]} {m_axi_rdata[7]} {m_axi_rdata[8]} {m_axi_rdata[9]} {m_axi_rdata[10]} {m_axi_rdata[11]} {m_axi_rdata[12]} {m_axi_rdata[13]} {m_axi_rdata[14]} {m_axi_rdata[15]} {m_axi_rdata[16]} {m_axi_rdata[17]} {m_axi_rdata[18]} {m_axi_rdata[19]} {m_axi_rdata[20]} {m_axi_rdata[21]} {m_axi_rdata[22]} {m_axi_rdata[23]} {m_axi_rdata[24]} {m_axi_rdata[25]} {m_axi_rdata[26]} {m_axi_rdata[27]} {m_axi_rdata[28]} {m_axi_rdata[29]} {m_axi_rdata[30]} {m_axi_rdata[31]} {m_axi_rdata[32]} {m_axi_rdata[33]} {m_axi_rdata[34]} {m_axi_rdata[35]} {m_axi_rdata[36]} {m_axi_rdata[37]} {m_axi_rdata[38]} {m_axi_rdata[39]} {m_axi_rdata[40]} {m_axi_rdata[41]} {m_axi_rdata[42]} {m_axi_rdata[43]} {m_axi_rdata[44]} {m_axi_rdata[45]} {m_axi_rdata[46]} {m_axi_rdata[47]} {m_axi_rdata[48]} {m_axi_rdata[49]} {m_axi_rdata[50]} {m_axi_rdata[51]} {m_axi_rdata[52]} {m_axi_rdata[53]} {m_axi_rdata[54]} {m_axi_rdata[55]} {m_axi_rdata[56]} {m_axi_rdata[57]} {m_axi_rdata[58]} {m_axi_rdata[59]} {m_axi_rdata[60]} {m_axi_rdata[61]} {m_axi_rdata[62]} {m_axi_rdata[63]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe170] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe170] -connect_debug_port u_ila_0/probe170 [get_nets [list {m_axi_rresp[0]} {m_axi_rresp[1]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe171] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe171] -connect_debug_port u_ila_0/probe171 [get_nets [list {m_axi_rvalid}]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe172] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe172] -connect_debug_port u_ila_0/probe172 [get_nets [list {m_axi_rlast}]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe173] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe173] -connect_debug_port u_ila_0/probe173 [get_nets [list {m_axi_rready}]] diff --git a/fpga/constraints/marked_debug.txt b/fpga/constraints/marked_debug.txt index 9b7927e10..3973fc451 100644 --- a/fpga/constraints/marked_debug.txt +++ b/fpga/constraints/marked_debug.txt @@ -1,7 +1,131 @@ -wally/wallypipelinedcore.sv: logic PCM -wally/wallypipelinedcore.sv: logic TrapM -wally/wallypipelinedcore.sv: logic InstrValidM -wally/wallypipelinedcore.sv: logic InstrM +lsu/lsu.sv: logic IEUAdrM +lsu/lsu.sv: logic WriteDataM lsu/lsu.sv: logic LSUHADDR -lsu/lsu.sv: logic LSUHREADY +lsu/lsu.sv: logic HRDATA lsu/lsu.sv: logic LSUHWDATA +lsu/lsu.sv: logic LSUHREADY +lsu/lsu.sv: logic LSUHWRITE +lsu/lsu.sv: logic LSUHSIZE +lsu/lsu.sv: logic LSUHBURST +lsu/lsu.sv: logic LSUHTRANS +lsu/lsu.sv: logic LSUHWSTRB +lsu/lsu.sv: logic IHAdrM +ieu/regfile.sv: logic rf +ieu/datapath.sv: logic RegWriteW +hazard/hazard.sv: logic BPPredWrongE +hazard/hazard.sv: logic LoadStallD +hazard/hazard.sv: logic FCvtIntStallD +hazard/hazard.sv: logic DivBusyE +hazard/hazard.sv: logic EcallFaultM +hazard/hazard.sv: logic WFIStallM +hazard/hazard.sv: logic StallF +hazard/hazard.sv: logic FlushD +cache/cachefsm.sv: statetype CurrState +wally/wallypipelinedcore.sv: logic TrapM +wally/wallypipelinedcore.sv: logic SrcAM +wally/wallypipelinedcore.sv: logic InstrM +wally/wallypipelinedcore.sv: logic PCM +wally/wallypipelinedcore.sv: logic MemRWM +wally/wallypipelinedcore.sv: logic InstrValidM +wally/wallypipelinedcore.sv: logic WriteDataM +wally/wallypipelinedcore.sv: logic IEUAdrM +wally/wallypipelinedcore.sv: logic HRDATA +ifu/spill.sv: statetype CurrState +ifu/ifu.sv: logic IFUStallF +ifu/ifu.sv: logic IFUHADDR +ifu/ifu.sv: logic HRDATA +ifu/ifu.sv: logic IFUHREADY +ifu/ifu.sv: logic IFUHWRITE +ifu/ifu.sv: logic IFUHSIZE +ifu/ifu.sv: logic IFUHBURST +ifu/ifu.sv: logic IFUHTRANS +ifu/ifu.sv: logic PCF +ifu/ifu.sv: logic PCNextF +ifu/ifu.sv: logic PCPF +ifu/ifu.sv: logic PostSpillInstrRawF +mmu/hptw.sv: logic ITLBWriteF +mmu/hptw.sv: statetype WalkerState +privileged/csrs.sv: logic CSRSReadValM +privileged/csrs.sv: logic SEPC_REGW +privileged/csrs.sv: logic MIP_REGW +privileged/csrs.sv: logic SSCRATCH_REGW +privileged/csrs.sv: logic SCAUSE_REGW +privileged/csr.sv: logic CSRReadValM +privileged/csr.sv: logic CSRSrcM +privileged/csr.sv: logic CSRWriteValM +privileged/csr.sv: logic MSTATUS_REGW +privileged/trap.sv: logic InstrMisalignedFaultM +privileged/trap.sv: logic BreakpointFaultM +privileged/trap.sv: logic LoadAccessFaultM +privileged/trap.sv: logic LoadPageFaultM +privileged/trap.sv: logic mretM +privileged/trap.sv: logic MIP_REGW +privileged/trap.sv: logic PendingIntsM +privileged/privileged.sv: logic CSRReadM +privileged/privileged.sv: logic InterruptM +privileged/csrc.sv: logic HPMCOUNTER_REGW +privileged/csri.sv: logic MExtInt +privileged/csri.sv: logic MIP_REGW_writeabl +privileged/csrm.sv: logic MIP_REGW +privileged/csrm.sv: logic MEPC_REGW +privileged/csrm.sv: logic MEDELEG_REGW +privileged/csrm.sv: logic MIDELEG_REGW +privileged/csrm.sv: logic MSCRATCH_REGW +privileged/csrm.sv: logic MCAUSE_REGW +uncore/uart_apb.sv: logic SIN +uncore/uart_apb.sv: logic SOUT +uncore/uart_apb.sv: logic OUT1b +uncore/uartPC16550D.sv: logic RBR +uncore/uartPC16550D.sv: logic FCR +uncore/uartPC16550D.sv: logic IER +uncore/uartPC16550D.sv: logic MCR +uncore/uartPC16550D.sv: logic baudpulse +uncore/uartPC16550D.sv: statetype rxstate +uncore/uartPC16550D.sv: logic rxfifo +uncore/uartPC16550D.sv: logic txfifo +uncore/uartPC16550D.sv: logic rxfifohead +uncore/uartPC16550D.sv: logic rxfifoentries +uncore/uartPC16550D.sv: logic RXBR +uncore/uartPC16550D.sv: logic rxtimeoutcnt +uncore/uartPC16550D.sv: logic rxparityerr +uncore/uartPC16550D.sv: logic rxdataready +uncore/uartPC16550D.sv: logic rxfifoempty +uncore/uartPC16550D.sv: logic rxdata +uncore/uartPC16550D.sv: logic RXerrbit +uncore/uartPC16550D.sv: logic rxfullbitunwrapped +uncore/uartPC16550D.sv: logic txdata +uncore/uartPC16550D.sv: logic txnextbit +uncore/uartPC16550D.sv: logic txfifoempty +uncore/uartPC16550D.sv: logic fifoenabled +uncore/uartPC16550D.sv: logic RXerr +uncore/uartPC16550D.sv: logic THRE +uncore/uartPC16550D.sv: logic rxdataavailintr +uncore/uartPC16550D.sv: logic intrID +uncore/uncore.sv: logic HSELEXTSDCD +uncore/plic_apb.sv: logic MExtInt +uncore/plic_apb.sv: logic Din +uncore/plic_apb.sv: logic requests +uncore/plic_apb.sv: logic intPriority +uncore/plic_apb.sv: logic intInProgress +uncore/plic_apb.sv: logic intThreshold +uncore/plic_apb.sv: logic intEn +uncore/plic_apb.sv: logic intClaim +uncore/plic_apb.sv: logic irqMatrix +uncore/plic_apb.sv: logic priorities_with_irqs +uncore/plic_apb.sv: logic max_priority_with_irqs +uncore/plic_apb.sv: logic irqs_at_max_priority +uncore/plic_apb.sv: logic threshMask +uncore/clint_apb.sv: logic MTIME +uncore/clint_apb.sv: logic MTIMECMP +ebu/ebu.sv: logic HCLK +ebu/ebu.sv: logic HREADY +ebu/ebu.sv: logic HRESP +ebu/ebu.sv: logic HADDR +ebu/ebu.sv: logic HWRITE +ebu/ebu.sv: logic HSIZE +ebu/ebu.sv: logic HBURST +ebu/ebu.sv: logic HPROT +ebu/ebu.sv: logic HTRANS +ebu/ebu.sv: logic HMASTLOC +ebu/buscachefsm.sv: busstatetype CurrState +ebu/busfsm.sv: busstatetype CurrState diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index a3c7eec47..c24c91b7d 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -96,7 +96,8 @@ if {$board=="ArtyA7"} { source ../constraints/small-debug.xdc } else { - source ../constraints/vcu-small-debug.xdc + #source ../constraints/vcu-small-debug.xdc + source ../constraints/debug4.xdc } diff --git a/fpga/generator/xlnx_ddr4-vcu118.tcl b/fpga/generator/xlnx_ddr4-vcu118.tcl index 2a0dc21fc..510c68678 100644 --- a/fpga/generator/xlnx_ddr4-vcu118.tcl +++ b/fpga/generator/xlnx_ddr4-vcu118.tcl @@ -38,7 +38,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \ CONFIG.C0.DDR4_AxiNarrowBurst {false} \ CONFIG.Reference_Clock {Differential} \ CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \ - CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {38} \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {50} \ CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \ CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \ CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \ From 5790dafdce923df67c46446d88de6bf98ca925f7 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 2 Aug 2023 13:02:28 -0500 Subject: [PATCH 04/24] Fixed constraint in VCU118. --- fpga/constraints/constraints-vcu118.xdc | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/fpga/constraints/constraints-vcu118.xdc b/fpga/constraints/constraints-vcu118.xdc index 7b70950a5..4d185f994 100644 --- a/fpga/constraints/constraints-vcu118.xdc +++ b/fpga/constraints/constraints-vcu118.xdc @@ -3,8 +3,6 @@ # mmcm_clkout0 is the clock output of the DDR4 memory interface / 4. # This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP. -create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O] - ##### GPI #### set_property PACKAGE_PIN BB24 [get_ports {GPI[0]}] set_property PACKAGE_PIN BF22 [get_ports {GPI[1]}] @@ -106,6 +104,11 @@ set_property IOSTANDARD LVCMOS18 [get_ports SDCCLK] set_property IOSTANDARD LVCMOS18 [get_ports {SDCCmd}] set_property PACKAGE_PIN AV15 [get_ports SDCCLK] set_property PACKAGE_PIN AY15 [get_ports {SDCCmd}] + +set_property PACKAGE_PIN AT15 [get_ports {SDCCD}] +set_property IOSTANDARD LVCMOS18 [get_ports {SDCCD}] +set_property PULLUP true [get_ports {SDCCD}] + set_property PULLUP true [get_ports {SDCDat[3]}] set_property PULLUP true [get_ports {SDCDat[2]}] set_property PULLUP true [get_ports {SDCDat[1]}] @@ -113,17 +116,17 @@ set_property PULLUP true [get_ports {SDCDat[0]}] set_property PULLUP true [get_ports {SDCCmd}] -set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}] -set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 21.000 [get_ports {SDCDat[*]}] +set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.500 [get_ports {SDCDat[*]}] +set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 21.000 [get_ports {SDCDat[*]}] -set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCCmd}] -set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 14.000 [get_ports {SDCCmd}] +set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.500 [get_ports {SDCCmd}] +set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 14.000 [get_ports {SDCCmd}] -set_output_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.000 [get_ports {SDCCmd}] -set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_ports {SDCCmd}] +set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {SDCCmd}] +set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 6.000 [get_ports {SDCCmd}] -set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK] +set_output_delay -clock [get_clocks mmcm_clkout1] 0.000 [get_ports SDCCLK] From fb1c1a18327e1cc5752e6440e2221bd4fce5ebd8 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 2 Aug 2023 16:14:04 -0500 Subject: [PATCH 05/24] Added new signals to the vcu118 debug4 ila to help figure out why the new linux build's hptw fails. --- fpga/constraints/debug4.xdc | 30 ++++++++++++++++++++++++++++++ fpga/generator/wally.tcl | 6 +++--- 2 files changed, 33 insertions(+), 3 deletions(-) diff --git a/fpga/constraints/debug4.xdc b/fpga/constraints/debug4.xdc index 78dc6caaa..f26ce6c91 100644 --- a/fpga/constraints/debug4.xdc +++ b/fpga/constraints/debug4.xdc @@ -717,3 +717,33 @@ set_property port_width 64 [get_debug_ports u_ila_0/probe138] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe138] connect_debug_port u_ila_0/probe138 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]] +create_debug_port u_ila_0 probe +set_property port_width 49 [get_debug_ports u_ila_0/probe139] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe139] +connect_debug_port u_ila_0/probe139 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[53]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe140] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe140] +connect_debug_port u_ila_0/probe140 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/ValidNonLeafPTE}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe141] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe141] +connect_debug_port u_ila_0/probe141 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/ValidLeafPTE}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe142] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe142] +connect_debug_port u_ila_0/probe142 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/ValidPTE}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe143] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe143] +connect_debug_port u_ila_0/probe143 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/LeafPTE}]] + + +create_debug_port u_ila_0 probe +set_property port_width 48 [get_debug_ports u_ila_0/probe144] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe144] +connect_debug_port u_ila_0/probe144 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[63]}]] diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index c24c91b7d..32baade79 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -69,7 +69,7 @@ exec rm -rf reports/* report_compile_order -constraints > reports/compile_order.rpt # this is elaboration not synthesis. -synth_design -rtl -name rtl_1 -flatten_hierarchy full +synth_design -rtl -name rtl_1 -flatten_hierarchy none report_clocks -file reports/clocks.rpt @@ -78,7 +78,7 @@ set_param messaging.defaultLimit 100000 # this does synthesis? -launch_runs synth_1 -jobs 4 +launch_runs synth_1 -jobs 16 wait_on_run synth_1 open_run synth_1 @@ -105,7 +105,7 @@ if {$board=="ArtyA7"} { #set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1] #set_property "steps.route_design.args.directive" "RuntimeOptimized" [get_runs impl_1] -launch_runs impl_1 +launch_runs impl_1 -jobs 16 wait_on_run impl_1 launch_runs impl_1 -to_step write_bitstream wait_on_run impl_1 From cab40e618f98b1c41d96de7b28f75aa8decbaa6d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 2 Aug 2023 16:51:32 -0500 Subject: [PATCH 06/24] Updateds to vcu118 constraints and device tree. --- fpga/generator/wave_config.wcfg | 172 +++++++++++++++++------------- linux/devicetree/wally-vcu118.dts | 20 +++- 2 files changed, 114 insertions(+), 78 deletions(-) diff --git a/fpga/generator/wave_config.wcfg b/fpga/generator/wave_config.wcfg index 81fc67f05..f87f68696 100644 --- a/fpga/generator/wave_config.wcfg +++ b/fpga/generator/wave_config.wcfg @@ -3,30 +3,27 @@ - + - - - + + + - - + + - + - FullPathName wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[63:0] PCM[63:0] HEXRADIX - true - STYLE_DIGITAL FullPathName @@ -78,6 +75,7 @@ CPU to LSU label + FullPathName wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[63:0] @@ -152,8 +150,8 @@ label FullPathName - wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0] - MEDELEG_REGW[63:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[11:0] + MEDELEG_REGW[11:0] HEXRADIX true STYLE_DIGITAL @@ -176,8 +174,8 @@ FullPathName - wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0] - MEDELEG_REGW[63:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[11:0] + MEDELEG_REGW[11:0] HEXRADIX true STYLE_DIGITAL @@ -269,6 +267,15 @@ dcache fsm + + FullPathName + wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[3:0] + CurrState[3:0] + HEXRADIX + true + STYLE_DIGITAL + dcache fsm + EBU label @@ -320,14 +327,6 @@ true STYLE_DIGITAL - - FullPathName - wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HWDATA[63:0] - HWDATA[63:0] - HEXRADIX - true - STYLE_DIGITAL - FullPathName wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HREADY @@ -655,13 +654,6 @@ hazards label - - FullPathName - wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/BPPredWrongE - BPPredWrongE - true - STYLE_DIGITAL - FullPathName wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/BreakpointFaultM @@ -676,20 +668,6 @@ true STYLE_DIGITAL - - FullPathName - wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/CSRWriteFencePendingDEM - CSRWriteFencePendingDEM - true - STYLE_DIGITAL - - - FullPathName - wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/DivBusyE - DivBusyE - true - STYLE_DIGITAL - FullPathName wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/EcallFaultM @@ -743,7 +721,6 @@ flush/stall label - FullPathName wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushD @@ -772,13 +749,6 @@ true STYLE_DIGITAL - - FullPathName - wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallD - StallD - true - STYLE_DIGITAL - FullPathName wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallE @@ -801,14 +771,6 @@ STYLE_DIGITAL - - FullPathName - wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[63:0] - csrs.SCAUSE_REGW[63:0] - HEXRADIX - true - STYLE_DIGITAL - FullPathName wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[63:0] @@ -822,7 +784,7 @@ label - label + FullPathName wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[3:0] CurrState[3:0] HEXRADIX @@ -831,7 +793,7 @@ STYLE_DIGITAL - label + FullPathName wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[2:0] CurrState[2:0] HEXRADIX @@ -856,10 +818,43 @@ STYLE_DIGITAL + + FullPathName + wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[3:0] + CurrState[3:0] + HEXRADIX + icache fsm + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[2:0] + CurrState[2:0] + HEXRADIX + ifu bus fsm + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[63:0] + PCNextF[63:0] + HEXRADIX + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[55:0] + PCPF[55:0] + HEXRADIX + true + STYLE_DIGITAL + TLB label - FullPathName wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/DTLBMissM @@ -889,6 +884,34 @@ STYLE_DIGITAL + + FullPathName + wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/DTLBMissM + DTLBMissM + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/DTLBWriteM + DTLBWriteM + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ITLBMissF + ITLBMissF + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ITLBWriteF + ITLBWriteF + true + STYLE_DIGITAL + FullPathName wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[63:0] @@ -897,14 +920,6 @@ true STYLE_DIGITAL - - FullPathName - wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[63:0] - SEPC_REGW[63:0] - HEXRADIX - true - STYLE_DIGITAL - FullPathName wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[63:0] @@ -929,12 +944,19 @@ true STYLE_DIGITAL - - FullPathName - wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.hptw/WalkerState[3:0] + + wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[3:0] WalkerState[3:0] HEXRADIX - true - STYLE_DIGITAL + + + wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[31:0] + LSUHADDR[31:0] + HEXRADIX + + + wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[63:0] + ReadDataM[63:0] + HEXRADIX diff --git a/linux/devicetree/wally-vcu118.dts b/linux/devicetree/wally-vcu118.dts index 224d4570f..a4794f0d0 100644 --- a/linux/devicetree/wally-vcu118.dts +++ b/linux/devicetree/wally-vcu118.dts @@ -21,8 +21,8 @@ cpus { #address-cells = <0x01>; #size-cells = <0x00>; - clock-frequency = <0x24AE230>; - timebase-frequency = <0x24AE230>; + clock-frequency = <0x2FAF080>; + timebase-frequency = <0x2FAF080>; cpu@0 { phandle = <0x01>; @@ -51,7 +51,7 @@ uart@10000000 { interrupts = <0x0a>; interrupt-parent = <0x03>; - clock-frequency = <0x24AE230>; + clock-frequency = <0x2FAF080>; reg = <0x00 0x10000000 0x00 0x100>; compatible = "ns16550a"; }; @@ -67,6 +67,20 @@ #address-cells = <0x00>; }; + mmc@13000 { + interrupts = <0x14>; + compatible = "riscv,axi-sd-card-1.0"; + reg = <0x00 0x13000 0x00 0x7F>; + fifo-depth = <256>; + bus-width = <4>; + interrupt-parent = <0x03>; + clock = <0x2FAF080>; + max-frequency = <0x989680>; + cap-sd-highspeed; + cap-mmc-highspeed; + no-sdio; + }; + clint@2000000 { interrupts-extended = <0x02 0x03 0x02 0x07>; reg = <0x00 0x2000000 0x00 0x10000>; From 0eac74ac7b866a439a05f5e53a456772a2c9f149 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 14 Aug 2023 15:43:12 -0500 Subject: [PATCH 07/24] Initial CMO implementation. Just adds control signals into the L1 caches. --- src/cache/cache.sv | 7 ++++--- src/cache/cachefsm.sv | 14 ++++++++++++-- src/ifu/ifu.sv | 3 ++- src/lsu/lsu.sv | 2 +- 4 files changed, 19 insertions(+), 7 deletions(-) diff --git a/src/cache/cache.sv b/src/cache/cache.sv index 3910333ed..145921ef0 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -38,6 +38,7 @@ module cache import cvw::*; #(parameter cvw_t P, input logic [1:0] CacheAtomic, // Atomic operation input logic FlushCache, // Flush all dirty lines back to memory input logic InvalidateCache, // Clear all valid bits + input logic [3:0] CMOp, // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero input logic [11:0] NextSet, // Virtual address, but we only use the lower 12 bits. input logic [PA_BITS-1:0] PAdr, // Physical address input logic [(WORDLEN-1)/8:0] ByteMask, // Which bytes to write (D$ only) @@ -75,7 +76,7 @@ module cache import cvw::*; #(parameter cvw_t P, logic [1:0] AdrSelMuxSel; logic [SETLEN-1:0] CacheSet; logic [LINELEN-1:0] LineWriteData; - logic ClearDirty, SetDirty, SetValid; + logic ClearDirty, SetDirty, SetValid, ClearValid; logic [LINELEN-1:0] ReadDataLineWay [NUMWAYS-1:0]; logic [NUMWAYS-1:0] HitWay, ValidWay; logic CacheHit; @@ -215,8 +216,8 @@ module cache import cvw::*; #(parameter cvw_t P, .FlushStage, .CacheRW, .CacheAtomic, .Stall, .CacheHit, .LineDirty, .CacheStall, .CacheCommitted, .CacheMiss, .CacheAccess, .SelAdr, - .ClearDirty, .SetDirty, .SetValid, .SelWriteback, .SelFlush, + .ClearDirty, .SetDirty, .SetValid, .ClearValid, .SelWriteback, .SelFlush, .FlushAdrCntEn, .FlushWayCntEn, .FlushCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelFetchBuffer, - .InvalidateCache, .CacheEn, .LRUWriteEn); + .InvalidateCache, .CMOp, .CacheEn, .LRUWriteEn); endmodule diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 6f7ff1500..e6ea6b595 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -40,6 +40,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( input logic [1:0] CacheAtomic, // Atomic operation input logic FlushCache, // Flush all dirty lines back to memory input logic InvalidateCache, // Clear all valid bits + input logic [3:0] CMOp, // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero // Bus controls input logic CacheBusAck, // Bus operation completed output logic [1:0] CacheBusRW, // [1] Read (cache line fetch) or [0] write bus (cache line writeback) @@ -54,8 +55,9 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( input logic FlushWayFlag, // On the last way for any set of a cache flush output logic SelAdr, // [0] SRAM reads from NextAdr, [1] SRAM reads from PAdr output logic SetValid, // Set the valid bit in the selected way and set - output logic ClearDirty, // Clear the dirty bit in the selected way and set + output logic ClearValid, // Clear the valid bit in the selected way and set output logic SetDirty, // Set the dirty bit in the selected way and set + output logic ClearDirty, // Clear the dirty bit in the selected way and set output logic SelWriteback, // Overrides cached tag check to select a specific way and set for writeback output logic LRUWriteEn, // Update the LRU state output logic SelFlush, // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr @@ -140,6 +142,13 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( (CurrState == STATE_FLUSH_WRITEBACK); // write enables internal to cache assign SetValid = CurrState == STATE_WRITE_LINE; + + // *** fix param later + //if (P.ZICBOM_SUPPORTED) + assign ClearValid = (CurrState == STATE_READY & CMOp[0]) | + (CurrState == STATE_WRITEBACK & CMOp[1]); + // *** end of fix me + // coverage off -item e 1 -fecexprrow 8 assign LRUWriteEn = (CurrState == STATE_READY & AnyHit) | (CurrState == STATE_WRITE_LINE) & ~FlushStage; @@ -147,8 +156,9 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( assign SetDirty = (CurrState == STATE_READY & AnyUpdateHit) | // exclusion-tag: icache SetDirty (CurrState == STATE_WRITE_LINE & (CacheRW[0])); assign ClearDirty = (CurrState == STATE_WRITE_LINE & ~(CacheRW[0])) | // exclusion-tag: icache ClearDirty - (CurrState == STATE_FLUSH & LineDirty); // This is wrong in a multicore snoop cache protocal. Dirty must be cleared concurrently and atomically with writeback. For single core cannot clear after writeback on bus ack and change flushadr. Clears the wrong set. + (CurrState == STATE_FLUSH & LineDirty) | // This is wrong in a multicore snoop cache protocal. Dirty must be cleared concurrently and atomically with writeback. For single core cannot clear after writeback on bus ack and change flushadr. Clears the wrong set. // Flush and eviction controls + (CurrState == STATE_WRITEBACK & (CMOp[1] | CMOp[2] | CMOp[3])); // *** fix me param assign SelWriteback = (CurrState == STATE_WRITEBACK & ~CacheBusAck) | (CurrState == STATE_READY & AnyMiss & LineDirty); diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index 95c75c3c7..2bceb6175 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -233,6 +233,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : '0; assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0; + // *** RT: Fix CMOp. Should be CMOpM. Also PAdr and NextSet are replaced with mux between PCPF/IEUAdrM and PCSpillNextF/IEUAdrE. cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.ICACHE_LINELENINBITS), .NUMLINES(P.ICACHE_WAYSIZEINBYTES*8/P.ICACHE_LINELENINBITS), .NUMWAYS(P.ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .READ_ONLY_CACHE(1)) @@ -249,7 +250,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( .CacheAtomic('0), .FlushCache('0), .NextSet(PCSpillNextF[11:0]), .PAdr(PCPF), - .CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM)); + .CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM), .CMOp('0)); ahbcacheinterface #(P.AHBW, P.LLEN, P.PA_BITS, WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW, 1) ahbcacheinterface(.HCLK(clk), .HRESETn(~reset), diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index a80fb055e..8c9ff05f7 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -276,7 +276,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( .CacheCommitted(DCacheCommittedM), .CacheBusAdr(DCacheBusAdr), .ReadDataWord(DCacheReadDataWordM), .FetchBuffer, .CacheBusRW(CacheBusRWTemp), - .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0)); + .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0), .CMOp(CMOpM)); assign DCacheStallM = CacheStall & ~IgnoreRequestTLB; assign CacheBusRW = CacheBusRWTemp; From 9f37fef145214d42c7c5884a61baa52fca9e6581 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 14 Aug 2023 16:39:18 -0500 Subject: [PATCH 08/24] The L1 D cache now supports cache line (block) invalidation and partial support for clean and flush. --- src/cache/cache.sv | 6 +++--- src/cache/cacheLRU.sv | 8 ++++++-- src/cache/cacheway.sv | 5 ++++- 3 files changed, 13 insertions(+), 6 deletions(-) diff --git a/src/cache/cache.sv b/src/cache/cache.sv index 145921ef0..b70f4d5e9 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -116,14 +116,14 @@ module cache import cvw::*; #(parameter cvw_t P, // Array of cache ways, along with victim, hit, dirty, and read merging logic cacheway #(P, PA_BITS, XLEN, NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0]( .clk, .reset, .CacheEn, .CacheSet, .PAdr, .LineWriteData, .LineByteMask, - .SetValid, .SetDirty, .ClearDirty, .SelWriteback, .VictimWay, + .SetValid, .ClearValid, .SetDirty, .ClearDirty, .SelWriteback, .VictimWay, .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .TagWay, .FlushStage, .InvalidateCache); // Select victim way for associative caches if(NUMWAYS > 1) begin:vict cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cacheLRU( - .clk, .reset, .CacheEn, .HitWay, .ValidWay, .VictimWay, .CacheSet, .LRUWriteEn, - .SetValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache, .FlushCache); + .clk, .reset, .FlushStage, .CacheEn, .HitWay, .ValidWay, .VictimWay, .CacheSet, .LRUWriteEn, + .SetValid, .ClearValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache, .FlushCache); end else assign VictimWay = 1'b1; // one hot. diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index 5fb00dc90..34ea59612 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -31,6 +31,7 @@ module cacheLRU #(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMLINES = 128) ( input logic clk, input logic reset, + input logic FlushStage, input logic CacheEn, // Enable the cache memory arrays. Disable hold read data constant input logic [NUMWAYS-1:0] HitWay, // Which way is valid and matches PAdr's tag input logic [NUMWAYS-1:0] ValidWay, // Which ways for a particular set are valid, ignores tag @@ -38,6 +39,7 @@ module cacheLRU input logic [SETLEN-1:0] PAdr, // Physical address input logic LRUWriteEn, // Update the LRU state input logic SetValid, // Set the dirty bit in the selected way and set + input logic ClearValid, // Clear the dirty bit in the selected way and set input logic InvalidateCache, // Clear all valid bits input logic FlushCache, // Flush all dirty lines back to memory output logic [NUMWAYS-1:0] VictimWay // LRU selects a victim to evict @@ -138,9 +140,11 @@ module cacheLRU // This is a two port memory. // Every cycle must read from CacheSet and each load/store must write the new LRU. always_ff @(posedge clk) begin - if (reset) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0; + if (reset | (InvalidateCache & ~FlushStage)) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0; if(CacheEn) begin - if(LRUWriteEn) + if(ClearValid & ~FlushStage) + LRUMemory[PAdr] <= '0; + else if(LRUWriteEn) LRUMemory[PAdr] <= NextLRU; if(LRUWriteEn & (PAdr == CacheSet)) CurrLRU <= #1 NextLRU; diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 4438ea2c7..240e66859 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -38,6 +38,7 @@ module cacheway import cvw::*; #(parameter cvw_t P, input logic [PA_BITS-1:0] PAdr, // Physical address input logic [LINELEN-1:0] LineWriteData, // Final data written to cache (D$ only) input logic SetValid, // Set the valid bit in the selected way and set + input logic ClearValid, // Clear the valid bit in the selected way and set input logic SetDirty, // Set the dirty bit in the selected way and set input logic ClearDirty, // Clear the dirty bit in the selected way and set input logic SelWriteback, // Overrides cached tag check to select a specific way and set for writeback @@ -69,6 +70,7 @@ module cacheway import cvw::*; #(parameter cvw_t P, logic [LINELEN/8-1:0] FinalByteMask; logic SetValidEN; logic SetValidWay; + logic ClearValidWay; logic SetDirtyWay; logic ClearDirtyWay; logic SelNonHit; @@ -97,6 +99,7 @@ module cacheway import cvw::*; #(parameter cvw_t P, ///////////////////////////////////////////////////////////////////////////////////////////// assign SetValidWay = SetValid & SelData; + assign ClearValidWay = ClearValid & SelData; assign SetDirtyWay = SetDirty & SelData; // exclusion-tag: icache SetDirtyWay assign ClearDirtyWay = ClearDirty & SelData; assign SelectedWriteWordEn = (SetValidWay | SetDirtyWay) & ~FlushStage; // exclusion-tag: icache SelectedWiteWordEn @@ -155,7 +158,7 @@ module cacheway import cvw::*; #(parameter cvw_t P, if(CacheEn) begin ValidWay <= #1 ValidBits[CacheSet]; if(InvalidateCache) ValidBits <= #1 '0; // exclusion-tag: dcache invalidateway - else if (SetValidEN) ValidBits[CacheSet] <= #1 SetValidWay; + else if (SetValidEN | (ClearValidWay & ~FlushStage)) ValidBits[CacheSet] <= #1 SetValidWay; end end From 528107753174c382bf883e689c8577252e4b1bc6 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 15 Aug 2023 18:17:15 -0500 Subject: [PATCH 09/24] More progress towards cmo. --- src/cache/cache.sv | 2 +- src/cache/cachefsm.sv | 19 ++++++++----------- 2 files changed, 9 insertions(+), 12 deletions(-) diff --git a/src/cache/cache.sv b/src/cache/cache.sv index b70f4d5e9..43e58083b 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -212,7 +212,7 @@ module cache import cvw::*; #(parameter cvw_t P, // Cache FSM ///////////////////////////////////////////////////////////////////////////////////////////// - cachefsm #(READ_ONLY_CACHE) cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck, + cachefsm #(P, READ_ONLY_CACHE) cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck, .FlushStage, .CacheRW, .CacheAtomic, .Stall, .CacheHit, .LineDirty, .CacheStall, .CacheCommitted, .CacheMiss, .CacheAccess, .SelAdr, diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index e6ea6b595..4a0f0cb0d 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -27,7 +27,8 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module cachefsm #(parameter READ_ONLY_CACHE = 0) ( +module cachefsm import cvw::*; #(parameter cvw_t P, + parameter READ_ONLY_CACHE = 0) ( input logic clk, input logic reset, // hazard and privilege unit @@ -110,9 +111,10 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( STATE_READY: if(InvalidateCache) NextState = STATE_READY; // exclusion-tag: dcache InvalidateCheck else if(FlushCache & ~READ_ONLY_CACHE) NextState = STATE_FLUSH; else if(AnyMiss & (READ_ONLY_CACHE | ~LineDirty)) NextState = STATE_FETCH; // exclusion-tag: icache FETCHStatement - else if(AnyMiss) /* & LineDirty */ NextState = STATE_WRITEBACK; // exclusion-tag: icache WRITEBACKStatement + else if(AnyMiss | CMOp[2] | CMOp[3]) /* & LineDirty */NextState = STATE_WRITEBACK; // exclusion-tag: icache WRITEBACKStatement else NextState = STATE_READY; - STATE_FETCH: if(CacheBusAck) NextState = STATE_WRITE_LINE; + STATE_FETCH: if(CacheBusAck & ~(CMOp[2] | CMOp[3]))) NextState = STATE_WRITE_LINE; + else (CacheBusAck) /* CMOp[2] | CMOp[3] */ NextState = STATE_READY; else NextState = STATE_FETCH; STATE_WRITE_LINE: NextState = STATE_READ_HOLD; STATE_READ_HOLD: if(Stall) NextState = STATE_READ_HOLD; @@ -142,13 +144,8 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( (CurrState == STATE_FLUSH_WRITEBACK); // write enables internal to cache assign SetValid = CurrState == STATE_WRITE_LINE; - - // *** fix param later - //if (P.ZICBOM_SUPPORTED) - assign ClearValid = (CurrState == STATE_READY & CMOp[0]) | - (CurrState == STATE_WRITEBACK & CMOp[1]); - // *** end of fix me - + assign ClearValid = P.ZICBOM_SUPPORTED & ((CurrState == STATE_READY & CMOp[0]) | + (CurrState == STATE_WRITEBACK & CMOp[1])); // coverage off -item e 1 -fecexprrow 8 assign LRUWriteEn = (CurrState == STATE_READY & AnyHit) | (CurrState == STATE_WRITE_LINE) & ~FlushStage; @@ -158,7 +155,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( assign ClearDirty = (CurrState == STATE_WRITE_LINE & ~(CacheRW[0])) | // exclusion-tag: icache ClearDirty (CurrState == STATE_FLUSH & LineDirty) | // This is wrong in a multicore snoop cache protocal. Dirty must be cleared concurrently and atomically with writeback. For single core cannot clear after writeback on bus ack and change flushadr. Clears the wrong set. // Flush and eviction controls - (CurrState == STATE_WRITEBACK & (CMOp[1] | CMOp[2] | CMOp[3])); // *** fix me param + (P.ZICBOM_SUPPORTED & CurrState == STATE_WRITEBACK & (CMOp[1] | CMOp[2] | CMOp[3])); assign SelWriteback = (CurrState == STATE_WRITEBACK & ~CacheBusAck) | (CurrState == STATE_READY & AnyMiss & LineDirty); From 624b3e3ab243af28a22db2cecf54e26a837a965e Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 16 Aug 2023 14:23:56 -0500 Subject: [PATCH 10/24] Added clean and flush to cache fsm. --- src/cache/cachefsm.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 4a0f0cb0d..9d819f000 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -120,7 +120,8 @@ module cachefsm import cvw::*; #(parameter cvw_t P, STATE_READ_HOLD: if(Stall) NextState = STATE_READ_HOLD; else NextState = STATE_READY; // exclusion-tag-start: icache case - STATE_WRITEBACK: if(CacheBusAck) NextState = STATE_FETCH; + STATE_WRITEBACK: if(CacheBusAck & (CMop[2] | CMOp[3])) NextState = STATE_READY; + else if(CacheBusAck) NextState = STATE_FETCH; else NextState = STATE_WRITEBACK; // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack. STATE_FLUSH: if(LineDirty) NextState = STATE_FLUSH_WRITEBACK; From f9df1fda23564feb7acd0ce129d653b01c5855fe Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 17 Aug 2023 12:46:40 -0500 Subject: [PATCH 11/24] CMOZ now implemented in the D cache. --- src/cache/cache.sv | 16 +++++++++++----- src/cache/cachefsm.sv | 14 ++++++++------ src/cache/cacheway.sv | 13 ++++++++++--- 3 files changed, 29 insertions(+), 14 deletions(-) diff --git a/src/cache/cache.sv b/src/cache/cache.sv index 43e58083b..bf751bc31 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -98,7 +98,8 @@ module cache import cvw::*; #(parameter cvw_t P, logic CacheEn; logic [LINELEN/8-1:0] LineByteMask; logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0] WordOffsetAddr; - + logic ZeroCacheLine; + logic [LINELEN-1:0] PreLineWriteData; genvar index; ///////////////////////////////////////////////////////////////////////////////////////////// @@ -116,7 +117,7 @@ module cache import cvw::*; #(parameter cvw_t P, // Array of cache ways, along with victim, hit, dirty, and read merging logic cacheway #(P, PA_BITS, XLEN, NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0]( .clk, .reset, .CacheEn, .CacheSet, .PAdr, .LineWriteData, .LineByteMask, - .SetValid, .ClearValid, .SetDirty, .ClearDirty, .SelWriteback, .VictimWay, + .SetValid, .ClearValid, .SetDirty, .ClearDirty, .ZeroCacheLine, .SelWriteback, .VictimWay, .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .TagWay, .FlushStage, .InvalidateCache); // Select victim way for associative caches @@ -160,6 +161,11 @@ module cache import cvw::*; #(parameter cvw_t P, ///////////////////////////////////////////////////////////////////////////////////////////// // Write Path ///////////////////////////////////////////////////////////////////////////////////////////// + if(P.ZICBOZ_SUPPORTED) begin : cboz_supported + mux2 #(LINELEN) WriteDataMux(FetchBuffer, '0, ZeroCacheLine, PreLineWriteData); + end else begin + assign PreLineWriteData = FetchBuffer; + end if(!READ_ONLY_CACHE) begin:WriteSelLogic logic [CACHEWORDSPERLINE-1:0] MemPAdrDecoded; logic [LINELEN/8-1:0] DemuxedByteMask, FetchBufferByteSel; @@ -174,14 +180,14 @@ module cache import cvw::*; #(parameter cvw_t P, // Merge write data into fetched cache line for store miss for(index = 0; index < LINELEN/8; index++) begin mux2 #(8) WriteDataMux(.d0(CacheWriteData[(8*index)%WORDLEN+7:(8*index)%WORDLEN]), - .d1(FetchBuffer[8*index+7:8*index]), .s(FetchBufferByteSel[index]), .y(LineWriteData[8*index+7:8*index])); + .d1(PreLineWriteData[8*index+7:8*index]), .s(FetchBufferByteSel[index] | ZeroCacheLine), .y(LineWriteData[8*index+7:8*index])); end assign LineByteMask = SetValid ? '1 : SetDirty ? DemuxedByteMask : '0; end else begin:WriteSelLogic // No need for this mux if the cache does not handle writes. - assign LineWriteData = FetchBuffer; + assign LineWriteData = PreLineWriteData; assign LineByteMask = '1; end @@ -216,7 +222,7 @@ module cache import cvw::*; #(parameter cvw_t P, .FlushStage, .CacheRW, .CacheAtomic, .Stall, .CacheHit, .LineDirty, .CacheStall, .CacheCommitted, .CacheMiss, .CacheAccess, .SelAdr, - .ClearDirty, .SetDirty, .SetValid, .ClearValid, .SelWriteback, .SelFlush, + .ClearDirty, .SetDirty, .SetValid, .ClearValid, .ZeroCacheLine, .SelWriteback, .SelFlush, .FlushAdrCntEn, .FlushWayCntEn, .FlushCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelFetchBuffer, .InvalidateCache, .CMOp, .CacheEn, .LRUWriteEn); diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 9d819f000..ce044569b 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -59,6 +59,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P, output logic ClearValid, // Clear the valid bit in the selected way and set output logic SetDirty, // Set the dirty bit in the selected way and set output logic ClearDirty, // Clear the dirty bit in the selected way and set + output logic ZeroCacheLine, // Write zeros to all bytes of cacheline output logic SelWriteback, // Overrides cached tag check to select a specific way and set for writeback output logic LRUWriteEn, // Update the LRU state output logic SelFlush, // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr @@ -113,14 +114,14 @@ module cachefsm import cvw::*; #(parameter cvw_t P, else if(AnyMiss & (READ_ONLY_CACHE | ~LineDirty)) NextState = STATE_FETCH; // exclusion-tag: icache FETCHStatement else if(AnyMiss | CMOp[2] | CMOp[3]) /* & LineDirty */NextState = STATE_WRITEBACK; // exclusion-tag: icache WRITEBACKStatement else NextState = STATE_READY; - STATE_FETCH: if(CacheBusAck & ~(CMOp[2] | CMOp[3]))) NextState = STATE_WRITE_LINE; - else (CacheBusAck) /* CMOp[2] | CMOp[3] */ NextState = STATE_READY; + STATE_FETCH: if(CacheBusAck & ~(CMOp[2] | CMOp[3])) NextState = STATE_WRITE_LINE; + else if(CacheBusAck) /* CMOp[2] | CMOp[3] */ NextState = STATE_READY; else NextState = STATE_FETCH; STATE_WRITE_LINE: NextState = STATE_READ_HOLD; STATE_READ_HOLD: if(Stall) NextState = STATE_READ_HOLD; else NextState = STATE_READY; // exclusion-tag-start: icache case - STATE_WRITEBACK: if(CacheBusAck & (CMop[2] | CMOp[3])) NextState = STATE_READY; + STATE_WRITEBACK: if(CacheBusAck & (CMOp[2] | CMOp[3])) NextState = STATE_READY; else if(CacheBusAck) NextState = STATE_FETCH; else NextState = STATE_WRITEBACK; // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack. @@ -144,19 +145,20 @@ module cachefsm import cvw::*; #(parameter cvw_t P, (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_WRITEBACK); // write enables internal to cache - assign SetValid = CurrState == STATE_WRITE_LINE; + assign SetValid = CurrState == STATE_WRITE_LINE | (CurrState == STATE_READY & CMOp[3]); assign ClearValid = P.ZICBOM_SUPPORTED & ((CurrState == STATE_READY & CMOp[0]) | (CurrState == STATE_WRITEBACK & CMOp[1])); // coverage off -item e 1 -fecexprrow 8 assign LRUWriteEn = (CurrState == STATE_READY & AnyHit) | (CurrState == STATE_WRITE_LINE) & ~FlushStage; // exclusion-tag-start: icache flushdirtycontrols - assign SetDirty = (CurrState == STATE_READY & AnyUpdateHit) | // exclusion-tag: icache SetDirty + assign SetDirty = (CurrState == STATE_READY & (AnyUpdateHit | CMOp[3])) | // exclusion-tag: icache SetDirty (CurrState == STATE_WRITE_LINE & (CacheRW[0])); assign ClearDirty = (CurrState == STATE_WRITE_LINE & ~(CacheRW[0])) | // exclusion-tag: icache ClearDirty (CurrState == STATE_FLUSH & LineDirty) | // This is wrong in a multicore snoop cache protocal. Dirty must be cleared concurrently and atomically with writeback. For single core cannot clear after writeback on bus ack and change flushadr. Clears the wrong set. // Flush and eviction controls - (P.ZICBOM_SUPPORTED & CurrState == STATE_WRITEBACK & (CMOp[1] | CMOp[2] | CMOp[3])); + (P.ZICBOM_SUPPORTED & CurrState == STATE_WRITEBACK & (CMOp[1] | CMOp[2] | CMOp[3])); + assign ZeroCacheLine = CurrState == STATE_READY & CMOp[3]; assign SelWriteback = (CurrState == STATE_WRITEBACK & ~CacheBusAck) | (CurrState == STATE_READY & AnyMiss & LineDirty); diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 240e66859..fb361977a 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -40,6 +40,7 @@ module cacheway import cvw::*; #(parameter cvw_t P, input logic SetValid, // Set the valid bit in the selected way and set input logic ClearValid, // Clear the valid bit in the selected way and set input logic SetDirty, // Set the dirty bit in the selected way and set + input logic ZeroCacheLine, // Write zeros to all bytes of a cache line input logic ClearDirty, // Clear the dirty bit in the selected way and set input logic SelWriteback, // Overrides cached tag check to select a specific way and set for writeback input logic SelFlush, // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr @@ -75,7 +76,13 @@ module cacheway import cvw::*; #(parameter cvw_t P, logic ClearDirtyWay; logic SelNonHit; logic SelData; - + logic SelNotHit2; + + if (P.ZICBOM_SUPPORTED) begin : cbologic + assign SelNotHit2 = SetValid & ~(ZeroCacheLine & HitWay); + end else begin : cbologic + assign SelNotHit2 = SetValid; + end if (!READ_ONLY_CACHE) begin:flushlogic logic FlushWayEn; @@ -86,10 +93,10 @@ module cacheway import cvw::*; #(parameter cvw_t P, // coverage off -item e 1 -fecexprrow 3 // nonzero ways will never see SelFlush=0 while FlushWay=1 since FlushWay only advances on a subset of SelFlush assertion cases. assign FlushWayEn = FlushWay & SelFlush; - assign SelNonHit = FlushWayEn | SetValid | SelWriteback; + assign SelNonHit = FlushWayEn | SelNotHit2 | SelWriteback; end else begin:flushlogic // no flush operation for read-only caches. assign SelTag = VictimWay; - assign SelNonHit = SetValid; + assign SelNonHit = SelNotHit2; end mux2 #(1) selectedwaymux(HitWay, SelTag, SelNonHit , SelData); From 072126b9679b0b99cc038b4636705e1f36ed729c Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 17 Aug 2023 16:57:54 -0500 Subject: [PATCH 12/24] Found first bug in CMO implementation. --- src/cache/cachefsm.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index ce044569b..5dfffe219 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -182,7 +182,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P, (CurrState == STATE_WRITEBACK & ~CacheBusAck) | (CurrState == STATE_FLUSH_WRITEBACK & ~CacheBusAck); - assign SelAdr = (CurrState == STATE_READY & (CacheRW[0] | AnyMiss)) | // exclusion-tag: icache SelAdrCauses // changes if store delay hazard removed + assign SelAdr = (CurrState == STATE_READY & (CacheRW[0] | AnyMiss | (|CMOp))) | // exclusion-tag: icache SelAdrCauses // changes if store delay hazard removed (CurrState == STATE_FETCH) | (CurrState == STATE_WRITEBACK) | (CurrState == STATE_WRITE_LINE) | From 9dcc70d6c19549b17e2769557a2a80431046b9c8 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 17 Aug 2023 17:58:49 -0500 Subject: [PATCH 13/24] Updated the hazard logic for CMO operations. --- src/ieu/controller.sv | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index ede8f258e..14bbc15b6 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -425,5 +425,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( // the synchronous DTIM cannot read immediately after write // a cache cannot read or write immediately after a write // atomic operations are also detected as MemRWD[1] - assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & P.DCACHE_SUPPORTED))); + //assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & P.DCACHE_SUPPORTED))); + // *** RT: Modify for ZICBOZ + assign StoreStallD = (MemRWE[0] | (|CMOpE & P.ZICBOM_SUPPORTED)) & ((MemRWD[1] | (MemRWD[0] & P.DCACHE_SUPPORTED) | (|CMOpD & P.ZICBOM_SUPPORTED))); endmodule From 21129dde71ed05bf98b2471930571450f29c0cbf Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 18 Aug 2023 11:32:30 -0500 Subject: [PATCH 14/24] Fixed cbo instruction decode. --- src/cache/cachefsm.sv | 10 +++++----- src/ieu/controller.sv | 4 ++-- src/ieu/extend.sv | 2 +- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 5dfffe219..60b5b9fd5 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -112,16 +112,16 @@ module cachefsm import cvw::*; #(parameter cvw_t P, STATE_READY: if(InvalidateCache) NextState = STATE_READY; // exclusion-tag: dcache InvalidateCheck else if(FlushCache & ~READ_ONLY_CACHE) NextState = STATE_FLUSH; else if(AnyMiss & (READ_ONLY_CACHE | ~LineDirty)) NextState = STATE_FETCH; // exclusion-tag: icache FETCHStatement - else if(AnyMiss | CMOp[2] | CMOp[3]) /* & LineDirty */NextState = STATE_WRITEBACK; // exclusion-tag: icache WRITEBACKStatement + else if(AnyMiss | CMOp[1] | CMOp[2]) /* & LineDirty */NextState = STATE_WRITEBACK; // exclusion-tag: icache WRITEBACKStatement else NextState = STATE_READY; - STATE_FETCH: if(CacheBusAck & ~(CMOp[2] | CMOp[3])) NextState = STATE_WRITE_LINE; - else if(CacheBusAck) /* CMOp[2] | CMOp[3] */ NextState = STATE_READY; + STATE_FETCH: if(CacheBusAck & ~(CMOp[1] | CMOp[2])) NextState = STATE_WRITE_LINE; + else if(CacheBusAck) /* CMOp[1] | CMOp[2] */ NextState = STATE_READY; else NextState = STATE_FETCH; STATE_WRITE_LINE: NextState = STATE_READ_HOLD; STATE_READ_HOLD: if(Stall) NextState = STATE_READ_HOLD; else NextState = STATE_READY; // exclusion-tag-start: icache case - STATE_WRITEBACK: if(CacheBusAck & (CMOp[2] | CMOp[3])) NextState = STATE_READY; + STATE_WRITEBACK: if(CacheBusAck & (CMOp[1] | CMOp[2])) NextState = STATE_READ_HOLD; else if(CacheBusAck) NextState = STATE_FETCH; else NextState = STATE_WRITEBACK; // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack. @@ -138,7 +138,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P, // com back to CPU assign CacheCommitted = (CurrState != STATE_READY) & ~(READ_ONLY_CACHE & CurrState == STATE_READ_HOLD); - assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss)) | // exclusion-tag: icache StallStates + assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss | CMOp[1] | CMOp[2])) | // exclusion-tag: icache StallStates (CurrState == STATE_FETCH) | (CurrState == STATE_WRITEBACK) | (CurrState == STATE_WRITE_LINE) | // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write. diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 14bbc15b6..ecb1e6076 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -228,7 +228,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( always_comb begin ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_0_1; // default: Illegal instruction case(OpD) - // RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_ALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MDU_Atomic_CMO_Illegal + // RegWrite_ImmSrc_ALUSrc(A_B)_MemRW_ResultSrc_Branch_ALUOp_Jump_ALUResultSrc_BaseW64_CSRRead_Privileged_Fence_MDU_Atomic_CMO_Illegal 7'b0000011: if (LFunctD) ControlsD = `CTRLW'b1_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0_0; // loads 7'b0000111: if (FLSFunctD) @@ -239,7 +239,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( else ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_0_0; // fence treated as nop end else if (CMOFunctD) begin - ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1_0; // CMO Instruction + ControlsD = `CTRLW'b0_101_01_00_000_0_0_0_0_0_0_0_0_0_00_1_0; // CMO Instruction end 7'b0010011: if (IFunctD) ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_0_0_0_0_0_00_0_0; // I-type ALU diff --git a/src/ieu/extend.sv b/src/ieu/extend.sv index bcda43e0a..4f7ee387f 100644 --- a/src/ieu/extend.sv +++ b/src/ieu/extend.sv @@ -47,7 +47,7 @@ module extend import cvw::*; #(parameter cvw_t P) ( // U-type (lui, auipc) 3'b100: ImmExtD = {{(P.XLEN-31){InstrD[31]}}, InstrD[30:12], 12'b0}; // Store Conditional: zero offset - 3'b101: if (P.A_SUPPORTED) ImmExtD = 0; + 3'b101: if (P.A_SUPPORTED | P.ZICBOM_SUPPORTED | P.ZICBOZ_SUPPORTED) ImmExtD = 0; else ImmExtD = undefined; default: ImmExtD = undefined; // undefined endcase From 5c408454b8403f255e5a30bbb608a7474fc93757 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 18 Aug 2023 14:48:21 -0500 Subject: [PATCH 15/24] Might have working cbo clean and flush instructions. --- src/cache/cache.sv | 11 +++++++---- src/cache/cachefsm.sv | 43 ++++++++++++++++++++++++++++--------------- src/cache/cacheway.sv | 8 ++++++-- 3 files changed, 41 insertions(+), 21 deletions(-) diff --git a/src/cache/cache.sv b/src/cache/cache.sv index bf751bc31..52b54029f 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -90,6 +90,8 @@ module cache import cvw::*; #(parameter cvw_t P, logic [NUMWAYS-1:0] FlushWay, NextFlushWay; logic FlushWayCntEn; logic SelWriteback; + logic SelCMOWriteback; + logic SelBothWriteback; logic LRUWriteEn; logic SelFlush; logic ResetOrFlushCntRst; @@ -116,8 +118,8 @@ module cache import cvw::*; #(parameter cvw_t P, // Array of cache ways, along with victim, hit, dirty, and read merging logic cacheway #(P, PA_BITS, XLEN, NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0]( - .clk, .reset, .CacheEn, .CacheSet, .PAdr, .LineWriteData, .LineByteMask, - .SetValid, .ClearValid, .SetDirty, .ClearDirty, .ZeroCacheLine, .SelWriteback, .VictimWay, + .clk, .reset, .CacheEn, .CMOp, .CacheSet, .PAdr, .LineWriteData, .LineByteMask, + .SetValid, .ClearValid, .SetDirty, .ClearDirty, .ZeroCacheLine, .SelWriteback, .SelCMOWriteback, .VictimWay, .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .TagWay, .FlushStage, .InvalidateCache); // Select victim way for associative caches @@ -153,10 +155,11 @@ module cache import cvw::*; #(parameter cvw_t P, .PAdr(WordOffsetAddr), .ReadDataLine, .ReadDataWord); // Bus address for fetch, writeback, or flush writeback + assign SelBothWriteback = SelWriteback | SelCMOWriteback; mux3 #(PA_BITS) CacheBusAdrMux(.d0({PAdr[PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}), .d1({Tag, PAdr[SETTOP-1:OFFSETLEN], {OFFSETLEN{1'b0}}}), .d2({Tag, FlushAdr, {OFFSETLEN{1'b0}}}), - .s({SelFlush, SelWriteback}), .y(CacheBusAdr)); + .s({SelFlush, SelBothWriteback}), .y(CacheBusAdr)); ///////////////////////////////////////////////////////////////////////////////////////////// // Write Path @@ -222,7 +225,7 @@ module cache import cvw::*; #(parameter cvw_t P, .FlushStage, .CacheRW, .CacheAtomic, .Stall, .CacheHit, .LineDirty, .CacheStall, .CacheCommitted, .CacheMiss, .CacheAccess, .SelAdr, - .ClearDirty, .SetDirty, .SetValid, .ClearValid, .ZeroCacheLine, .SelWriteback, .SelFlush, + .ClearDirty, .SetDirty, .SetValid, .ClearValid, .ZeroCacheLine, .SelWriteback, .SelCMOWriteback, .SelFlush, .FlushAdrCntEn, .FlushWayCntEn, .FlushCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelFetchBuffer, .InvalidateCache, .CMOp, .CacheEn, .LRUWriteEn); diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 60b5b9fd5..6d36b78ba 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -61,6 +61,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P, output logic ClearDirty, // Clear the dirty bit in the selected way and set output logic ZeroCacheLine, // Write zeros to all bytes of cacheline output logic SelWriteback, // Overrides cached tag check to select a specific way and set for writeback + output logic SelCMOWriteback, // Overrides cached tag check to select a specific way and set for writeback for both data and tag output logic LRUWriteEn, // Update the LRU state output logic SelFlush, // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr output logic FlushAdrCntEn, // Enable the counter for Flush Adr @@ -83,7 +84,11 @@ module cachefsm import cvw::*; #(parameter cvw_t P, STATE_READ_HOLD, // required for back to back reads. structural hazard on writting SRAM // flush cache STATE_FLUSH, - STATE_FLUSH_WRITEBACK} statetype; + STATE_FLUSH_WRITEBACK, + // CMO states + STATE_CMO_WRITEBACK, + STATE_CMO_DONE + } statetype; statetype CurrState, NextState; @@ -112,17 +117,17 @@ module cachefsm import cvw::*; #(parameter cvw_t P, STATE_READY: if(InvalidateCache) NextState = STATE_READY; // exclusion-tag: dcache InvalidateCheck else if(FlushCache & ~READ_ONLY_CACHE) NextState = STATE_FLUSH; else if(AnyMiss & (READ_ONLY_CACHE | ~LineDirty)) NextState = STATE_FETCH; // exclusion-tag: icache FETCHStatement - else if(AnyMiss | CMOp[1] | CMOp[2]) /* & LineDirty */NextState = STATE_WRITEBACK; // exclusion-tag: icache WRITEBACKStatement + else if(AnyMiss) /* & LineDirty */ NextState = STATE_WRITEBACK; // exclusion-tag: icache WRITEBACKStatement + else if((CMOp[1] | CMOp[2]) & CacheHit) NextState = STATE_CMO_WRITEBACK; else NextState = STATE_READY; - STATE_FETCH: if(CacheBusAck & ~(CMOp[1] | CMOp[2])) NextState = STATE_WRITE_LINE; - else if(CacheBusAck) /* CMOp[1] | CMOp[2] */ NextState = STATE_READY; + STATE_FETCH: if(CacheBusAck) NextState = STATE_WRITE_LINE; + else if(CacheBusAck) NextState = STATE_READY; else NextState = STATE_FETCH; STATE_WRITE_LINE: NextState = STATE_READ_HOLD; STATE_READ_HOLD: if(Stall) NextState = STATE_READ_HOLD; else NextState = STATE_READY; // exclusion-tag-start: icache case - STATE_WRITEBACK: if(CacheBusAck & (CMOp[1] | CMOp[2])) NextState = STATE_READ_HOLD; - else if(CacheBusAck) NextState = STATE_FETCH; + STATE_WRITEBACK: if(CacheBusAck) NextState = STATE_FETCH; else NextState = STATE_WRITEBACK; // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack. STATE_FLUSH: if(LineDirty) NextState = STATE_FLUSH_WRITEBACK; @@ -131,36 +136,42 @@ module cachefsm import cvw::*; #(parameter cvw_t P, STATE_FLUSH_WRITEBACK: if(CacheBusAck & ~FlushFlag) NextState = STATE_FLUSH; else if(CacheBusAck) NextState = STATE_READ_HOLD; else NextState = STATE_FLUSH_WRITEBACK; + + STATE_CMO_WRITEBACK: if(CacheBusAck & (CMOp[1] | CMOp[2])) NextState = STATE_CMO_DONE; + else NextState = STATE_CMO_WRITEBACK; // exclusion-tag-end: icache case default: NextState = STATE_READY; endcase end // com back to CPU - assign CacheCommitted = (CurrState != STATE_READY) & ~(READ_ONLY_CACHE & CurrState == STATE_READ_HOLD); + assign CacheCommitted = (CurrState != STATE_READY) & ~(READ_ONLY_CACHE & (CurrState == STATE_READ_HOLD | CurrState == STATE_CMO_DONE)); assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss | CMOp[1] | CMOp[2])) | // exclusion-tag: icache StallStates (CurrState == STATE_FETCH) | (CurrState == STATE_WRITEBACK) | (CurrState == STATE_WRITE_LINE) | // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write. (CurrState == STATE_FLUSH) | - (CurrState == STATE_FLUSH_WRITEBACK); + (CurrState == STATE_FLUSH_WRITEBACK) | + (CurrState == STATE_CMO_WRITEBACK); // write enables internal to cache - assign SetValid = CurrState == STATE_WRITE_LINE | (CurrState == STATE_READY & CMOp[3]); + assign SetValid = CurrState == STATE_WRITE_LINE | + (CurrState == STATE_READY & CMOp[3]); // *** RT: NOT completely right has to be a hit assign ClearValid = P.ZICBOM_SUPPORTED & ((CurrState == STATE_READY & CMOp[0]) | - (CurrState == STATE_WRITEBACK & CMOp[1])); + (CurrState == STATE_CMO_DONE & CMOp[2])); // coverage off -item e 1 -fecexprrow 8 assign LRUWriteEn = (CurrState == STATE_READY & AnyHit) | (CurrState == STATE_WRITE_LINE) & ~FlushStage; // exclusion-tag-start: icache flushdirtycontrols - assign SetDirty = (CurrState == STATE_READY & (AnyUpdateHit | CMOp[3])) | // exclusion-tag: icache SetDirty + assign SetDirty = (CurrState == STATE_READY & (AnyUpdateHit | CMOp[3])) | // exclusion-tag: icache SetDirty *** NOT completely right has to be a hit for CMOp[3] (CurrState == STATE_WRITE_LINE & (CacheRW[0])); assign ClearDirty = (CurrState == STATE_WRITE_LINE & ~(CacheRW[0])) | // exclusion-tag: icache ClearDirty (CurrState == STATE_FLUSH & LineDirty) | // This is wrong in a multicore snoop cache protocal. Dirty must be cleared concurrently and atomically with writeback. For single core cannot clear after writeback on bus ack and change flushadr. Clears the wrong set. // Flush and eviction controls - (P.ZICBOM_SUPPORTED & CurrState == STATE_WRITEBACK & (CMOp[1] | CMOp[2] | CMOp[3])); - assign ZeroCacheLine = CurrState == STATE_READY & CMOp[3]; + (P.ZICBOM_SUPPORTED & CurrState == STATE_CMO_DONE & (CMOp[1] | CMOp[2])); + assign ZeroCacheLine = CurrState == STATE_READY & CMOp[3]; // *** RT: NOT completely right assign SelWriteback = (CurrState == STATE_WRITEBACK & ~CacheBusAck) | (CurrState == STATE_READY & AnyMiss & LineDirty); + assign SelCMOWriteback = CurrState == STATE_CMO_WRITEBACK; assign SelFlush = (CurrState == STATE_READY & FlushCache) | (CurrState == STATE_FLUSH) | @@ -179,13 +190,15 @@ module cachefsm import cvw::*; #(parameter cvw_t P, (CurrState == STATE_FETCH & ~CacheBusAck) | (CurrState == STATE_WRITEBACK & CacheBusAck); assign CacheBusRW[0] = (CurrState == STATE_READY & AnyMiss & LineDirty) | // exclusion-tag: icache CacheBusW - (CurrState == STATE_WRITEBACK & ~CacheBusAck) | - (CurrState == STATE_FLUSH_WRITEBACK & ~CacheBusAck); + (CurrState == STATE_WRITEBACK & ~CacheBusAck) | + (CurrState == STATE_FLUSH_WRITEBACK & ~CacheBusAck) | + (P.ZICBOM_SUPPORTED & CurrState == STATE_CMO_WRITEBACK & (CMOp[1] | CMOp[2]) & ~CacheBusAck); assign SelAdr = (CurrState == STATE_READY & (CacheRW[0] | AnyMiss | (|CMOp))) | // exclusion-tag: icache SelAdrCauses // changes if store delay hazard removed (CurrState == STATE_FETCH) | (CurrState == STATE_WRITEBACK) | (CurrState == STATE_WRITE_LINE) | + (CurrState == STATE_CMO_WRITEBACK) | resetDelay; assign SelFetchBuffer = CurrState == STATE_WRITE_LINE | CurrState == STATE_READ_HOLD; assign CacheEn = (~Stall | FlushCache | AnyMiss) | (CurrState != STATE_READY) | reset | InvalidateCache; // exclusion-tag: dcache CacheEn diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index fb361977a..85d2b36ab 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -33,6 +33,7 @@ module cacheway import cvw::*; #(parameter cvw_t P, input logic clk, input logic reset, input logic FlushStage, // Pipeline flush of second stage (prevent writes and bus operations) + input logic [3:0] CMOp, // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero input logic CacheEn, // Enable the cache memory arrays. Disable hold read data constant input logic [$clog2(NUMLINES)-1:0] CacheSet, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr input logic [PA_BITS-1:0] PAdr, // Physical address @@ -43,6 +44,7 @@ module cacheway import cvw::*; #(parameter cvw_t P, input logic ZeroCacheLine, // Write zeros to all bytes of a cache line input logic ClearDirty, // Clear the dirty bit in the selected way and set input logic SelWriteback, // Overrides cached tag check to select a specific way and set for writeback + input logic SelCMOWriteback, // Overrides cached tag check to select a specific way and set for writeback for both data and tag input logic SelFlush, // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr input logic VictimWay, // LRU selected this way as victim to evict input logic FlushWay, // This way is selected for flush and possible writeback if dirty @@ -78,7 +80,7 @@ module cacheway import cvw::*; #(parameter cvw_t P, logic SelData; logic SelNotHit2; - if (P.ZICBOM_SUPPORTED) begin : cbologic + if (P.ZICBOZ_SUPPORTED) begin : cbologic assign SelNotHit2 = SetValid & ~(ZeroCacheLine & HitWay); end else begin : cbologic assign SelNotHit2 = SetValid; @@ -93,7 +95,9 @@ module cacheway import cvw::*; #(parameter cvw_t P, // coverage off -item e 1 -fecexprrow 3 // nonzero ways will never see SelFlush=0 while FlushWay=1 since FlushWay only advances on a subset of SelFlush assertion cases. assign FlushWayEn = FlushWay & SelFlush; + // *** RT: This is slopy. I should refactor to have the fsm issue two types of writeback commands assign SelNonHit = FlushWayEn | SelNotHit2 | SelWriteback; + //assign SelNonHit = FlushWayEn | SelNotHit2 | SelWriteback; end else begin:flushlogic // no flush operation for read-only caches. assign SelTag = VictimWay; assign SelNonHit = SelNotHit2; @@ -124,7 +128,7 @@ module cacheway import cvw::*; #(parameter cvw_t P, .din(PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidEN)); // AND portion of distributed tag multiplexer - assign TagWay = SelTag ? ReadTag : '0; // AND part of AOMux + assign TagWay = SelData ? ReadTag : '0; // AND part of AOMux assign DirtyWay = SelTag & Dirty & ValidWay; assign HitWay = ValidWay & (ReadTag == PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]); From 4eeba9bed92fea2914c544a45507d32fe7cdf5f1 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 18 Aug 2023 15:59:39 -0500 Subject: [PATCH 16/24] Added cbom test to custom. Needs to be moved to wally-riscv-arch-tests. --- src/lsu/lsu.sv | 4 +- tests/custom/simple/Makefile | 2 +- tests/custom/simple/cbom.s | 351 +++++++++++++++++++++++++++++++++++ tests/custom/simple/header.h | 1 + tests/custom/simple/main.c | 3 +- 5 files changed, 358 insertions(+), 3 deletions(-) create mode 100644 tests/custom/simple/cbom.s diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 8c9ff05f7..aeadec262 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -185,7 +185,9 @@ module lsu import cvw::*; #(parameter cvw_t P) ( ///////////////////////////////////////////////////////////////////////////////////////////// if(P.ZICSR_SUPPORTED == 1) begin : dmmu logic DisableTranslation; // During HPTW walk or D$ flush disable virtual memory address translation + logic WriteAccessM; assign DisableTranslation = SelHPTW | FlushDCacheM; + assign WriteAccessM = PreLSURWM[0] | (|CMOpM); mmu #(.P(P), .TLB_ENTRIES(P.DTLB_ENTRIES), .IMMU(0)) dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, .DisableTranslation, .VAdr(IHAdrM), .Size(LSUFunct3M[1:0]), @@ -197,7 +199,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, // *** these faults need to be supressed during hptw. .UpdateDA(DataUpdateDAM), .AtomicAccessM(|LSUAtomicM), .ExecuteAccessF(1'b0), - .WriteAccessM(PreLSURWM[0]), .ReadAccessM(PreLSURWM[1]), + .WriteAccessM, .ReadAccessM(PreLSURWM[1]), .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW); end else begin // No MMU, so no PMA/page faults and no address translation diff --git a/tests/custom/simple/Makefile b/tests/custom/simple/Makefile index f85aedd5c..2c8c2bdab 100644 --- a/tests/custom/simple/Makefile +++ b/tests/custom/simple/Makefile @@ -4,7 +4,7 @@ ROOT := .. LIBRARY_DIRS := ${ROOT}/crt0 LIBRARY_FILES := crt0 -MARCH :=-march=rv64imfdc +MARCH :=-march=rv64imfdczicbom MABI :=-mabi=lp64d LINKER := ${ROOT}/linker8000-0000.x LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map diff --git a/tests/custom/simple/cbom.s b/tests/custom/simple/cbom.s new file mode 100644 index 000000000..2cd90949a --- /dev/null +++ b/tests/custom/simple/cbom.s @@ -0,0 +1,351 @@ +# Written: ross1728@gmail.com Rose Thompson 17 August 2023 +# Modified: +# Purpose: Tests the 3 Zicbom cache instructions which all operate on cacheline +# granularity blocks of memory. Invalidate: Clears valid and dirty bits +# and does not write back. Clean: Writes back dirty cacheline if needed +# and clears dirty bit. Does NOT clear valid bit. Flush: Cleans and then +# Invalidates. These operations apply to all caches in the memory system. +# The tests are divided into three parts one for the data cache, instruction cache +# and checks to verify the uncached regions of memory cause exceptions. +# ----------- +# Copyright (c) 2020. RISC-V International. All rights reserved. +# SPDX-License-Identifier: BSD-3-Clause +# ----------- +# +# This assembly file tests the fence.i instruction of the RISC-V Zifencei extension. +# + +.section .text +.globl CBOMTest +.type CBOMTest, @function +CBOMTest: + # *** TODO + # first need to discover the length of the cacheline. + # for now assume it is 64 bytes + + addi sp, sp, -16 + sd s0, 0(sp) + sd ra, 8(sp) + + la s0, signature + + ################################################################################ + # INVALIDATE D$ + ################################################################################ + + # theory of operation + # 1. Read several cachelines of data from memory into the d cache and copy to a second region of memory + # 2. Then verify the second region has the same data + # 3. Invalidate the second region + # 4. Verify the second region has the original invalid data + # DON'T batch each step. We want to see the transition between cachelines. The current should be invalidated + # but the next should have the copied data. + + # step 1 +CBOMTest_inval_step1: + la a0, SourceData + la a1, Destination1 + li a2, 64 + jal ra, memcpy8 + + # step 2 +CBOMTest_inval_step2: + la a0, SourceData + la a1, Destination1 + li a2, 64 + jal ra, memcmp8 + sd a0, 0(s0) # should be -1 + addi s0, s0, 8 + + # step 3 +CBOMTest_inval_step3: + la a1, Destination1 + cbo.inval (a1) + # step 4 (should be Invalid) + la a0, DeadBeafData1 + la a1, Destination1 + li a2, 8 + jal ra, memcmp8 + sd a0, 0(s0) # should be -1 + addi s0, s0, 8 + + # step 4 next line (should still be valid) +CBOMTest_inval_step4: + la a0, SourceData+64 + la a1, Destination1+64 + li a2, 8 + jal ra, memcmp8 + sd a0, 0(s0) # should be -1 + addi s0, s0, 8 + + # step 3 (Invalidate all remaining lines) +CBOMTest_inval_step3_all: + la a1, Destination1+64 + cbo.inval (a1) + cbo.inval (a1) # verify invalidating an already non present line does not cause an issue. + la a1, Destination1+128 + cbo.inval (a1) + la a1, Destination1+192 + cbo.inval (a1) + la a1, Destination1+256 + cbo.inval (a1) + la a1, Destination1+320 + cbo.inval (a1) + la a1, Destination1+384 + cbo.inval (a1) + la a1, Destination1+448 + cbo.inval (a1) + + # step 4 All should be invalid +CBOMTest_inval_step4_all: + la a0, DeadBeafData1 + la a1, Destination1 + li a2, 64 + jal ra, memcmp8 + sd a0, 0(s0) # should be -1 + addi s0, s0, 8 + + ################################################################################ + # Clean D$ + ################################################################################ + + # theory of operation + # 1. Read several cachelines of data from memory into the d cache and copy to a second region of memory + # 2. Then verify the second region has the same data + # 3. Invalidate the second region + # 4. Verify the second region has the original invalid data + # 5. Repeat step 1 + # 6. Clean cachelines + # 7. Verify the second region has the same data + # 8. Invalidate the second region + # 9. Verify again but this time it should contain the same data + # DON'T batch each step. We want to see the transition between cachelines. The current should be invalidated + # but the next should have the copied data. + + # step 1 +CBOMTest_clean_step1: + la a0, SourceData + la a1, Destination2 + li a2, 64 + jal ra, memcpy8 + + # step 2 +CBOMTest_clean_step2: + la a0, SourceData + la a1, Destination2 + li a2, 64 + jal ra, memcmp8 + sd a0, 0(s0) # should be -1 + addi s0, s0, 8 + + # step 3 +CBOMTest_clean_step3: + la a1, Destination2 + cbo.inval (a1) + la a1, Destination2+64 + cbo.inval (a1) + la a1, Destination2+128 + cbo.inval (a1) + la a1, Destination2+192 + cbo.inval (a1) + la a1, Destination2+256 + cbo.inval (a1) + la a1, Destination2+320 + cbo.inval (a1) + la a1, Destination2+384 + cbo.inval (a1) + la a1, Destination2+448 + cbo.inval (a1) + + # step 4 All should be invalid +CBOMTest_clean_step4: + la a0, DeadBeafData1 + la a1, Destination2 + li a2, 64 + jal ra, memcmp8 + sd a0, 0(s0) # should be -1 + addi s0, s0, 8 + + # step 5 +CBOMTest_clean_step5: + la a0, SourceData + la a1, Destination2 + li a2, 64 + jal ra, memcpy8 + + # step 6 only clean 1 line +CBOMTest_clean_step6: + la a1, Destination2 + cbo.clean (a1) + + # step 7 only check that 1 line +CBOMTest_clean_step7: + la a0, SourceData + la a1, Destination2 + li a2, 8 + jal ra, memcmp8 + sd a0, 0(s0) # should be -1 + addi s0, s0, 8 + + # step 8 invalidate that 1 line and the next +CBOMTest_clean_step8: + la a1, Destination2 + cbo.inval (a1) + la a1, Destination2+64 + cbo.inval (a1) + + # step 9 that 1 line should contain the valid data +CBOMTest_clean_step9_line1: + la a0, SourceData + la a1, Destination2 + li a2, 8 + jal ra, memcmp8 + sd a0, 0(s0) # should be -1 + addi s0, s0, 8 + + # step 9 the next should contain the invalid data +CBOMTest_clean_step9_line2: + la a0, DeadBeafData1 + la a1, Destination2+64 + li a2, 8 + jal ra, memcmp8 + sd a0, 0(s0) # should be -1 + addi s0, s0, 8 + + # step 5 # now recopy the one we just corrupted +CBOMTest_clean_step5_recopy_line2: + la a0, SourceData+64 + la a1, Destination2+64 + li a2, 8 + jal ra, memcpy8 + + # step 6 # clean the remaining +CBOMTest_clean_step6_clean_all: + la a1, Destination2+64 + cbo.clean (a1) + la a1, Destination2+128 + cbo.clean (a1) + la a1, Destination2+192 + cbo.clean (a1) + la a1, Destination2+256 + cbo.clean (a1) + la a1, Destination2+320 + cbo.clean (a1) + la a1, Destination2+384 + cbo.clean (a1) + la a1, Destination2+448 + cbo.clean (a1) + + # step 8 # invalidate all remaining +CBOMTest_clean_step7_invalidate_all: + la a1, Destination2 + cbo.inval (a1) + la a1, Destination2+64 + cbo.inval (a1) + la a1, Destination2+128 + cbo.inval (a1) + la a1, Destination2+192 + cbo.inval (a1) + la a1, Destination2+256 + cbo.inval (a1) + la a1, Destination2+320 + cbo.inval (a1) + la a1, Destination2+384 + cbo.inval (a1) + la a1, Destination2+448 + cbo.inval (a1) + + # step 9 # check all +CBOMTest_clean_step9_check_all: + la a0, SourceData + la a1, Destination2 + li a2, 64 + jal ra, memcmp8 + sd a0, 0(s0) # should be -1 + addi s0, s0, 8 + + ld s0, 0(sp) + ld ra, 8(sp) + addi sp, sp, 16 + ret + + +.section .text +.type memcpy8, @function +memcpy8: + # a0 is the source + # a1 is the dst + # a2 is the number of 8 byte words + mv t0, a0 + mv t1, a1 + li t2, 0 +memcpy8_loop: + ld t3, 0(t0) + sd t3, 0(t1) + addi t0, t0, 8 + addi t1, t1, 8 + addi t2, t2, 1 + blt t2, a2, memcpy8_loop + ret + +.section .text +.type memcmp8, @function +# returns which index mismatch, -1 if none +memcmp8: + # a0 is the source1 + # a1 is the source2 + # a2 is the number of 8 byte words + mv t0, a0 + mv t1, a1 + li t2, 0 +memcmp8_loop: + ld t3, 0(t0) + ld t4, 0(t1) + bne t3, t4, memcmp8_ne + addi t0, t0, 8 + addi t1, t1, 8 + addi t2, t2, 1 + blt t2, a2, memcmp8_loop + li a0, -1 + ret +memcmp8_ne: + mv a0, t2 + ret + + + +.data +.align 7 + +DeadBeafData1: + .fill 64, 8, 0xdeadbeefdeadbeef +SourceData: + .int 0, 1, 2, 3, 4, 5, 6, 7 + .int 8, 9, 10, 11, 12, 13, 14, 15 + .int 16, 17, 18, 19, 20, 21, 22, 23 + .int 24, 25, 26, 27, 28, 29, 30, 31 + .int 32, 33, 34, 35, 36, 37, 38, 39 + .int 40, 41, 42, 43, 44, 45, 46, 47 + .int 48, 49, 50, 51, 52, 53, 54, 55 + .int 56, 57, 58, 59, 60, 61, 62, 63 + .int 64, 65, 66, 67, 68, 69, 70, 71 + .int 72, 73, 74, 75, 76, 77, 79, 79 + .int 80, 81, 82, 83, 84, 85, 86, 87 + .int 88, 89, 90, 91, 92, 93, 94, 95 + .int 96, 97, 98, 99, 100, 101, 102, 103 + .int 104, 105, 106, 107, 108, 109, 110, 111 + .int 112, 113, 114, 115, 116, 117, 118, 119 + .int 120, 121, 122, 123, 124, 125, 126, 127 + +Destination1: + .fill 64, 8, 0xdeadbeefdeadbeef +Destination2: + .fill 64, 8, 0xdeadbeefdeadbeef +Destination3: + .fill 64, 8, 0xdeadbeefdeadbeef +Destination4: + .fill 64, 8, 0xdeadbeefdeadbeef + +signature: + .fill 16, 8, 0x0bad0bad0bad0bad + diff --git a/tests/custom/simple/header.h b/tests/custom/simple/header.h index 973bdd59a..a237e8c17 100644 --- a/tests/custom/simple/header.h +++ b/tests/custom/simple/header.h @@ -12,4 +12,5 @@ void global_hist_3_space_test(); void global_hist_4_space_test(); void global_hist_6_space_test(); void oneLoopTest(); +void CBOMTest(); #endif diff --git a/tests/custom/simple/main.c b/tests/custom/simple/main.c index bebd96f6b..d1af33ab1 100644 --- a/tests/custom/simple/main.c +++ b/tests/custom/simple/main.c @@ -8,7 +8,8 @@ int main(){ global_hist_3_space_test(); global_hist_2_space_test(); global_hist_1_space_test(); - global_hist_0_space_test(); + global_hist_0_space_test(); + CBOMTest(); int res = 1; if (res < 0) { fail(); From fc3fccafe9213fa3f060afe74a92b1bb2a1c2a4b Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 18 Aug 2023 16:32:22 -0500 Subject: [PATCH 17/24] Now we have invalidate, clean, and flush working. --- src/cache/cachefsm.sv | 4 +- tests/custom/simple/cbom.s | 76 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 78 insertions(+), 2 deletions(-) diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 6d36b78ba..8628937e7 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -157,7 +157,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P, assign SetValid = CurrState == STATE_WRITE_LINE | (CurrState == STATE_READY & CMOp[3]); // *** RT: NOT completely right has to be a hit assign ClearValid = P.ZICBOM_SUPPORTED & ((CurrState == STATE_READY & CMOp[0]) | - (CurrState == STATE_CMO_DONE & CMOp[2])); + (CurrState == STATE_CMO_WRITEBACK & CMOp[2] & CacheBusAck)); // coverage off -item e 1 -fecexprrow 8 assign LRUWriteEn = (CurrState == STATE_READY & AnyHit) | (CurrState == STATE_WRITE_LINE) & ~FlushStage; @@ -167,7 +167,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P, assign ClearDirty = (CurrState == STATE_WRITE_LINE & ~(CacheRW[0])) | // exclusion-tag: icache ClearDirty (CurrState == STATE_FLUSH & LineDirty) | // This is wrong in a multicore snoop cache protocal. Dirty must be cleared concurrently and atomically with writeback. For single core cannot clear after writeback on bus ack and change flushadr. Clears the wrong set. // Flush and eviction controls - (P.ZICBOM_SUPPORTED & CurrState == STATE_CMO_DONE & (CMOp[1] | CMOp[2])); + (P.ZICBOM_SUPPORTED & CurrState == STATE_CMO_WRITEBACK & (CMOp[1] | CMOp[2]) & CacheBusAck); assign ZeroCacheLine = CurrState == STATE_READY & CMOp[3]; // *** RT: NOT completely right assign SelWriteback = (CurrState == STATE_WRITEBACK & ~CacheBusAck) | (CurrState == STATE_READY & AnyMiss & LineDirty); diff --git a/tests/custom/simple/cbom.s b/tests/custom/simple/cbom.s index 2cd90949a..e2c89284e 100644 --- a/tests/custom/simple/cbom.s +++ b/tests/custom/simple/cbom.s @@ -264,6 +264,77 @@ CBOMTest_clean_step9_check_all: sd a0, 0(s0) # should be -1 addi s0, s0, 8 + ################################################################################ + # Flush D$ line + ################################################################################ + + # theory of operation + # 1. Read several cachelines of data from memory into the d cache and copy to a second region of memory + # 2. Then verify the second region has the same data + # 3. For flush there is no way to create a negative control. We will flush 1 cache line + # 4. Verify whole region + # 5. Flush the remaining lines + # 6. Verify whole region + + # step 1 +CBOMTest_flush_step1: + la a0, SourceData + la a1, Destination3 + li a2, 64 + jal ra, memcpy8 + + # step 2 All should be valid +CBOMTest_flush_step2_verify: + la a0, SourceData + la a1, Destination3 + li a2, 64 + jal ra, memcmp8 + sd a0, 0(s0) # should be -1 + addi s0, s0, 8 + + # step 3 # flush 1 line +CBOMTest_flush_step3: + la a1, Destination3 + cbo.flush (a1) + + # step 4 +CBOMTest_flush_step4_verify: + la a0, SourceData + la a1, Destination3 + li a2, 64 + jal ra, memcmp8 + sd a0, 0(s0) # should be -1 + addi s0, s0, 8 + + # step 5 +CBOMTest_flush_step5_flush_all: + la a1, Destination3 + cbo.flush (a1) + la a1, Destination3+64 + cbo.flush (a1) + la a1, Destination3+128 + cbo.flush (a1) + la a1, Destination3+192 + cbo.flush (a1) + la a1, Destination3+256 + cbo.flush (a1) + la a1, Destination3+320 + cbo.flush (a1) + la a1, Destination3+384 + cbo.flush (a1) + la a1, Destination3+448 + cbo.flush (a1) + + # step 6 +CBOMTest_flush_step6_verify: + la a0, SourceData + la a1, Destination3 + li a2, 64 + jal ra, memcmp8 + sd a0, 0(s0) # should be -1 + addi s0, s0, 8 + + ld s0, 0(sp) ld ra, 8(sp) addi sp, sp, 16 @@ -349,3 +420,8 @@ Destination4: signature: .fill 16, 8, 0x0bad0bad0bad0bad + +ExceptedSignature: + .fill 13, 8, 0xFFFFFFFFFFFFFFFF + .fill 3, 8, 0x0bad0bad0bad0bad + From 05d590b0b95fc63585501ae5e958ff07390e725d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 18 Aug 2023 16:36:13 -0500 Subject: [PATCH 18/24] Fixed issue when with flush miss. --- src/cache/cachefsm.sv | 2 +- tests/custom/simple/cbom.s | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 8628937e7..5be35a1a8 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -146,7 +146,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P, // com back to CPU assign CacheCommitted = (CurrState != STATE_READY) & ~(READ_ONLY_CACHE & (CurrState == STATE_READ_HOLD | CurrState == STATE_CMO_DONE)); - assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss | CMOp[1] | CMOp[2])) | // exclusion-tag: icache StallStates + assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss | ((CMOp[1] | CMOp[2]) & CacheHit))) | // exclusion-tag: icache StallStates (CurrState == STATE_FETCH) | (CurrState == STATE_WRITEBACK) | (CurrState == STATE_WRITE_LINE) | // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write. diff --git a/tests/custom/simple/cbom.s b/tests/custom/simple/cbom.s index e2c89284e..814b776a6 100644 --- a/tests/custom/simple/cbom.s +++ b/tests/custom/simple/cbom.s @@ -156,6 +156,15 @@ CBOMTest_clean_step3: cbo.inval (a1) la a1, Destination2+448 cbo.inval (a1) + cbo.inval (a1) + cbo.inval (a1) + cbo.inval (a1) + cbo.inval (a1) + cbo.inval (a1) + cbo.inval (a1) + cbo.inval (a1) + cbo.inval (a1) + cbo.inval (a1) # step 4 All should be invalid CBOMTest_clean_step4: @@ -235,6 +244,14 @@ CBOMTest_clean_step6_clean_all: cbo.clean (a1) la a1, Destination2+448 cbo.clean (a1) + cbo.clean (a1) + cbo.clean (a1) + cbo.clean (a1) + cbo.clean (a1) + cbo.clean (a1) + cbo.clean (a1) + cbo.clean (a1) + cbo.clean (a1) # step 8 # invalidate all remaining CBOMTest_clean_step7_invalidate_all: @@ -324,6 +341,11 @@ CBOMTest_flush_step5_flush_all: cbo.flush (a1) la a1, Destination3+448 cbo.flush (a1) + cbo.flush (a1) + cbo.flush (a1) + cbo.flush (a1) + cbo.flush (a1) + cbo.flush (a1) # step 6 CBOMTest_flush_step6_verify: From 5ed096e4bc417e1ead4655c041c3434fe6264c00 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 21 Aug 2023 11:46:21 -0500 Subject: [PATCH 19/24] Made a bunch of progress towards getting cbo instructions tested. --- .../references/WALLY-cbom-01.reference_output | 528 ++++++++++++++++++ .../rv64i_m/privilege/src/WALLY-cbom-01.S | 475 ++++++++++++++++ 2 files changed, 1003 insertions(+) create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-cbom-01.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-cbom-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-cbom-01.reference_output new file mode 100644 index 000000000..5ec4c1a60 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-cbom-01.reference_output @@ -0,0 +1,528 @@ +deadbeef # destination 1 +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +00000000 # destination 2 +00000001 +00000002 +00000003 +00000004 +00000005 +00000006 +00000007 +00000008 +00000009 +0000000a +0000000b +0000000c +0000000d +0000000e +0000000f +00000010 +00000011 +00000012 +00000013 +00000014 +00000015 +00000016 +00000017 +00000018 +00000019 +0000001a +0000001b +0000001c +0000001d +0000001e +0000001f +00000020 +00000021 +00000022 +00000023 +00000024 +00000025 +00000026 +00000027 +00000028 +00000029 +0000002a +0000002b +0000002c +0000002d +0000002e +0000002f +00000030 +00000031 +00000032 +00000033 +00000034 +00000035 +00000036 +00000037 +00000038 +00000039 +0000003a +0000003b +0000003c +0000003d +0000003e +0000003f +00000040 +00000041 +00000042 +00000043 +00000044 +00000045 +00000046 +00000047 +00000048 +00000049 +0000004a +0000004b +0000004c +0000004d +0000004e +0000004f +00000050 +00000051 +00000052 +00000053 +00000054 +00000055 +00000056 +00000057 +00000058 +00000059 +0000005a +0000005b +0000005c +0000005d +0000005e +0000005f +00000060 +00000061 +00000062 +00000063 +00000064 +00000065 +00000066 +00000067 +00000068 +00000069 +0000006a +0000006b +0000006c +0000006d +0000006e +0000006f +00000070 +00000071 +00000072 +00000073 +00000074 +00000075 +00000076 +00000077 +00000078 +00000079 +0000007a +0000007b +0000007c +0000007d +0000007e +0000007f +00000000 # destination 3 +00000001 +00000002 +00000003 +00000004 +00000005 +00000006 +00000007 +00000008 +00000009 +0000000a +0000000b +0000000c +0000000d +0000000e +0000000f +00000010 +00000011 +00000012 +00000013 +00000014 +00000015 +00000016 +00000017 +00000018 +00000019 +0000001a +0000001b +0000001c +0000001d +0000001e +0000001f +00000020 +00000021 +00000022 +00000023 +00000024 +00000025 +00000026 +00000027 +00000028 +00000029 +0000002a +0000002b +0000002c +0000002d +0000002e +0000002f +00000030 +00000031 +00000032 +00000033 +00000034 +00000035 +00000036 +00000037 +00000038 +00000039 +0000003a +0000003b +0000003c +0000003d +0000003e +0000003f +00000040 +00000041 +00000042 +00000043 +00000044 +00000045 +00000046 +00000047 +00000048 +00000049 +0000004a +0000004b +0000004c +0000004d +0000004e +0000004f +00000050 +00000051 +00000052 +00000053 +00000054 +00000055 +00000056 +00000057 +00000058 +00000059 +0000005a +0000005b +0000005c +0000005d +0000005e +0000005f +00000060 +00000061 +00000062 +00000063 +00000064 +00000065 +00000066 +00000067 +00000068 +00000069 +0000006a +0000006b +0000006c +0000006d +0000006e +0000006f +00000070 +00000071 +00000072 +00000073 +00000074 +00000075 +00000076 +00000077 +00000078 +00000079 +0000007a +0000007b +0000007c +0000007d +0000007e +0000007f +deadbeef # destination 4 +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +ffffffff # signature The test writes -1 for correct answers and the a positive integer for incorrect copies. +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +0bad0bad # controls +0bad0bad +0bad0bad diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S new file mode 100644 index 000000000..b3f22aca7 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S @@ -0,0 +1,475 @@ +/////////////////////////////////////////// +// +// WALLY-cache-management-tests +// invalidate, clean, and flush +// +// Author: Rose Thompson +// +// Created 18 August 2023 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +# Purpose: Tests the 3 Zicbom cache instructions which all operate on cacheline +# granularity blocks of memory. Invalidate: Clears valid and dirty bits +# and does not write back. Clean: Writes back dirty cacheline if needed +# and clears dirty bit. Does NOT clear valid bit. Flush: Cleans and then +# Invalidates. These operations apply to all caches in the memory system. +# The tests are divided into three parts one for the data cache, instruction cache +# and checks to verify the uncached regions of memory cause exceptions. +# ----------- +# Copyright (c) 2020. RISC-V International. All rights reserved. +# SPDX-License-Identifier: BSD-3-Clause +# ----------- +# +# This assembly file tests the cbo.inval, cbo.clean, and cbo.flush instructions of the RISC-V Zicbom extension. +# + +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64I_Zicbom") +# Test code region +.section .text.init +.globl rvtest_entry_point + +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",cbo.inval) + +RVMODEL_IO_WRITE_STR(x31, "# Test Begin\n") + +CBOMTest: + # *** TODO + # first need to discover the length of the cacheline. + # for now assume it is 64 bytes + + #addi sp, sp, -16 + #sd s0, 0(sp) + #sd ra, 8(sp) + + la s0, signature + + ################################################################################ + # INVALIDATE D$ + ################################################################################ + + # theory of operation + # 1. Read several cachelines of data from memory into the d cache and copy to a second region of memory + # 2. Then verify the second region has the same data + # 3. Invalidate the second region + # 4. Verify the second region has the original invalid data + # DON'T batch each step. We want to see the transition between cachelines. The current should be invalidated + # but the next should have the copied data. + + # step 1 +CBOMTest_inval_step1: + la a0, SourceData + la a1, Destination1 + li a2, 64 + jal ra, memcpy8 + + # step 2 +CBOMTest_inval_step2: + la a0, SourceData + la a1, Destination1 + li a2, 64 + jal ra, memcmp8 + sd a0, 0(s0) # should be -1 + addi s0, s0, 8 + + # step 3 +CBOMTest_inval_step3: + la a1, Destination1 + cbo.inval (a1) + # step 4 (should be Invalid) + la a0, DeadBeafData1 + la a1, Destination1 + li a2, 8 + jal ra, memcmp8 + sd a0, 0(s0) # should be -1 + addi s0, s0, 8 + + # step 4 next line (should still be valid) +CBOMTest_inval_step4: + la a0, SourceData+64 + la a1, Destination1+64 + li a2, 8 + jal ra, memcmp8 + sd a0, 0(s0) # should be -1 + addi s0, s0, 8 + + # step 3 (Invalidate all remaining lines) +CBOMTest_inval_step3_all: + la a1, Destination1+64 + cbo.inval (a1) + cbo.inval (a1) # verify invalidating an already non present line does not cause an issue. + la a1, Destination1+128 + cbo.inval (a1) + la a1, Destination1+192 + cbo.inval (a1) + la a1, Destination1+256 + cbo.inval (a1) + la a1, Destination1+320 + cbo.inval (a1) + la a1, Destination1+384 + cbo.inval (a1) + la a1, Destination1+448 + cbo.inval (a1) + + # step 4 All should be invalid +CBOMTest_inval_step4_all: + la a0, DeadBeafData1 + la a1, Destination1 + li a2, 64 + jal ra, memcmp8 + sd a0, 0(s0) # should be -1 + addi s0, s0, 8 + + ################################################################################ + # Clean D$ + ################################################################################ + + # theory of operation + # 1. Read several cachelines of data from memory into the d cache and copy to a second region of memory + # 2. Then verify the second region has the same data + # 3. Invalidate the second region + # 4. Verify the second region has the original invalid data + # 5. Repeat step 1 + # 6. Clean cachelines + # 7. Verify the second region has the same data + # 8. Invalidate the second region + # 9. Verify again but this time it should contain the same data + # DON'T batch each step. We want to see the transition between cachelines. The current should be invalidated + # but the next should have the copied data. + + # step 1 +CBOMTest_clean_step1: + la a0, SourceData + la a1, Destination2 + li a2, 64 + jal ra, memcpy8 + + # step 2 +CBOMTest_clean_step2: + la a0, SourceData + la a1, Destination2 + li a2, 64 + jal ra, memcmp8 + sd a0, 0(s0) # should be -1 + addi s0, s0, 8 + + # step 3 +CBOMTest_clean_step3: + la a1, Destination2 + cbo.inval (a1) + la a1, Destination2+64 + cbo.inval (a1) + la a1, Destination2+128 + cbo.inval (a1) + la a1, Destination2+192 + cbo.inval (a1) + la a1, Destination2+256 + cbo.inval (a1) + la a1, Destination2+320 + cbo.inval (a1) + la a1, Destination2+384 + cbo.inval (a1) + la a1, Destination2+448 + cbo.inval (a1) + cbo.inval (a1) + cbo.inval (a1) + cbo.inval (a1) + cbo.inval (a1) + cbo.inval (a1) + cbo.inval (a1) + cbo.inval (a1) + cbo.inval (a1) + cbo.inval (a1) + + # step 4 All should be invalid +CBOMTest_clean_step4: + la a0, DeadBeafData1 + la a1, Destination2 + li a2, 64 + jal ra, memcmp8 + sd a0, 0(s0) # should be -1 + addi s0, s0, 8 + + # step 5 +CBOMTest_clean_step5: + la a0, SourceData + la a1, Destination2 + li a2, 64 + jal ra, memcpy8 + + # step 6 only clean 1 line +CBOMTest_clean_step6: + la a1, Destination2 + cbo.clean (a1) + + # step 7 only check that 1 line +CBOMTest_clean_step7: + la a0, SourceData + la a1, Destination2 + li a2, 8 + jal ra, memcmp8 + sd a0, 0(s0) # should be -1 + addi s0, s0, 8 + + # step 8 invalidate that 1 line and the next +CBOMTest_clean_step8: + la a1, Destination2 + cbo.inval (a1) + la a1, Destination2+64 + cbo.inval (a1) + + # step 9 that 1 line should contain the valid data +CBOMTest_clean_step9_line1: + la a0, SourceData + la a1, Destination2 + li a2, 8 + jal ra, memcmp8 + sd a0, 0(s0) # should be -1 + addi s0, s0, 8 + + # step 9 the next should contain the invalid data +CBOMTest_clean_step9_line2: + la a0, DeadBeafData1 + la a1, Destination2+64 + li a2, 8 + jal ra, memcmp8 + sd a0, 0(s0) # should be -1 + addi s0, s0, 8 + + # step 5 # now recopy the one we just corrupted +CBOMTest_clean_step5_recopy_line2: + la a0, SourceData+64 + la a1, Destination2+64 + li a2, 8 + jal ra, memcpy8 + + # step 6 # clean the remaining +CBOMTest_clean_step6_clean_all: + la a1, Destination2+64 + cbo.clean (a1) + la a1, Destination2+128 + cbo.clean (a1) + la a1, Destination2+192 + cbo.clean (a1) + la a1, Destination2+256 + cbo.clean (a1) + la a1, Destination2+320 + cbo.clean (a1) + la a1, Destination2+384 + cbo.clean (a1) + la a1, Destination2+448 + cbo.clean (a1) + cbo.clean (a1) + cbo.clean (a1) + cbo.clean (a1) + cbo.clean (a1) + cbo.clean (a1) + cbo.clean (a1) + cbo.clean (a1) + cbo.clean (a1) + + # step 8 # invalidate all remaining +CBOMTest_clean_step7_invalidate_all: + la a1, Destination2 + cbo.inval (a1) + la a1, Destination2+64 + cbo.inval (a1) + la a1, Destination2+128 + cbo.inval (a1) + la a1, Destination2+192 + cbo.inval (a1) + la a1, Destination2+256 + cbo.inval (a1) + la a1, Destination2+320 + cbo.inval (a1) + la a1, Destination2+384 + cbo.inval (a1) + la a1, Destination2+448 + cbo.inval (a1) + + # step 9 # check all +CBOMTest_clean_step9_check_all: + la a0, SourceData + la a1, Destination2 + li a2, 64 + jal ra, memcmp8 + sd a0, 0(s0) # should be -1 + addi s0, s0, 8 + + ################################################################################ + # Flush D$ line + ################################################################################ + + # theory of operation + # 1. Read several cachelines of data from memory into the d cache and copy to a second region of memory + # 2. Then verify the second region has the same data + # 3. For flush there is no way to create a negative control. We will flush 1 cache line + # 4. Verify whole region + # 5. Flush the remaining lines + # 6. Verify whole region + + # step 1 +CBOMTest_flush_step1: + la a0, SourceData + la a1, Destination3 + li a2, 64 + jal ra, memcpy8 + + # step 2 All should be valid +CBOMTest_flush_step2_verify: + la a0, SourceData + la a1, Destination3 + li a2, 64 + jal ra, memcmp8 + sd a0, 0(s0) # should be -1 + addi s0, s0, 8 + + # step 3 # flush 1 line +CBOMTest_flush_step3: + la a1, Destination3 + cbo.flush (a1) + + # step 4 +CBOMTest_flush_step4_verify: + la a0, SourceData + la a1, Destination3 + li a2, 64 + jal ra, memcmp8 + sd a0, 0(s0) # should be -1 + addi s0, s0, 8 + + # step 5 +CBOMTest_flush_step5_flush_all: + la a1, Destination3 + cbo.flush (a1) + la a1, Destination3+64 + cbo.flush (a1) + la a1, Destination3+128 + cbo.flush (a1) + la a1, Destination3+192 + cbo.flush (a1) + la a1, Destination3+256 + cbo.flush (a1) + la a1, Destination3+320 + cbo.flush (a1) + la a1, Destination3+384 + cbo.flush (a1) + la a1, Destination3+448 + cbo.flush (a1) + cbo.flush (a1) + cbo.flush (a1) + cbo.flush (a1) + cbo.flush (a1) + cbo.flush (a1) + + # step 6 +CBOMTest_flush_step6_verify: + la a0, SourceData + la a1, Destination3 + li a2, 64 + jal ra, memcmp8 + sd a0, 0(s0) # should be -1 + addi s0, s0, 8 + + + #ld s0, 0(sp) + #ld ra, 8(sp) + #addi sp, sp, 16 + #ret +RVMODEL_HALT + + +.type memcpy8, @function +memcpy8: + # a0 is the source + # a1 is the dst + # a2 is the number of 8 byte words + mv t0, a0 + mv t1, a1 + li t2, 0 +memcpy8_loop: + ld t3, 0(t0) + sd t3, 0(t1) + addi t0, t0, 8 + addi t1, t1, 8 + addi t2, t2, 1 + blt t2, a2, memcpy8_loop + ret + +.type memcmp8, @function +# returns which index mismatch, -1 if none +memcmp8: + # a0 is the source1 + # a1 is the source2 + # a2 is the number of 8 byte words + mv t0, a0 + mv t1, a1 + li t2, 0 +memcmp8_loop: + ld t3, 0(t0) + ld t4, 0(t1) + bne t3, t4, memcmp8_ne + addi t0, t0, 8 + addi t1, t1, 8 + addi t2, t2, 1 + blt t2, a2, memcmp8_loop + li a0, -1 + ret +memcmp8_ne: + mv a0, t2 + ret + +RVTEST_CODE_END + + +RVTEST_DATA_BEGIN +# Input data section. +#.data +.align 7 + +DeadBeafData1: + .fill 128, 4, 0xdeadbeef +SourceData: + .int 0, 1, 2, 3, 4, 5, 6, 7 + .int 8, 9, 10, 11, 12, 13, 14, 15 + .int 16, 17, 18, 19, 20, 21, 22, 23 + .int 24, 25, 26, 27, 28, 29, 30, 31 + .int 32, 33, 34, 35, 36, 37, 38, 39 + .int 40, 41, 42, 43, 44, 45, 46, 47 + .int 48, 49, 50, 51, 52, 53, 54, 55 + .int 56, 57, 58, 59, 60, 61, 62, 63 + .int 64, 65, 66, 67, 68, 69, 70, 71 + .int 72, 73, 74, 75, 76, 77, 79, 79 + .int 80, 81, 82, 83, 84, 85, 86, 87 + .int 88, 89, 90, 91, 92, 93, 94, 95 + .int 96, 97, 98, 99, 100, 101, 102, 103 + .int 104, 105, 106, 107, 108, 109, 110, 111 + .int 112, 113, 114, 115, 116, 117, 118, 119 + .int 120, 121, 122, 123, 124, 125, 126, 127 + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN + .fill 28, 4, 0xdeadbeef # this is annoying, but RVMODEL_DATA_END and BEGIN insert + # 4 bytes. This needs to be aligned to a cacheline + +.align 6 +Destination1: + .fill 128, 4, 0xdeadbeef +Destination2: + .fill 128, 4, 0xdeadbeef +Destination3: + .fill 128, 4, 0xdeadbeef +Destination4: + .fill 128, 4, 0xdeadbeef + +signature: + .fill 128, 4, 0xdeadbeef + +RVMODEL_DATA_END + From d4c6ba627d70384cc2585b5e9290d28a21f9461a Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 21 Aug 2023 12:55:07 -0500 Subject: [PATCH 20/24] Working CBO tests for 64 bit! --- testbench/tests.vh | 1 + .../rv64i_m/privilege/Makefrag | 1 + .../references/WALLY-cbom-01.reference_output | 46 ++++++++++++++++++- .../rv64i_m/privilege/src/WALLY-cbom-01.S | 6 +-- 4 files changed, 50 insertions(+), 4 deletions(-) diff --git a/testbench/tests.vh b/testbench/tests.vh index 116d39424..06c4cbe5a 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -1936,6 +1936,7 @@ string arch64zbs[] = '{ string wally64priv[] = '{ `WALLYTEST, "rv64i_m/privilege/src/WALLY-csr-permission-s-01.S", + "rv64i_m/privilege/src/WALLY-cbom-01.S", "rv64i_m/privilege/src/WALLY-csr-permission-u-01.S", "rv64i_m/privilege/src/WALLY-mie-01.S", "rv64i_m/privilege/src/WALLY-minfo-01.S", diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag index 319c5d930..6b13612ce 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag @@ -56,6 +56,7 @@ target_tests_nosim = \ WALLY-trap-u-01 \ WALLY-status-fp-enabled-01 \ WALLY-wfi-01 \ + WALLY-cbom-01 \ # unclear why status-fp-enabled and wfi aren't simulating ok diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-cbom-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-cbom-01.reference_output index 5ec4c1a60..a44010745 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-cbom-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-cbom-01.reference_output @@ -1,3 +1,31 @@ +deadbeef # begin_signature +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef deadbeef # destination 1 deadbeef deadbeef @@ -523,6 +551,22 @@ ffffffff ffffffff ffffffff ffffffff -0bad0bad # controls +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +0bad0bad # controls +0bad0bad +0bad0bad +0bad0bad 0bad0bad 0bad0bad diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S index b3f22aca7..374ee1c88 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S @@ -444,7 +444,7 @@ SourceData: .int 48, 49, 50, 51, 52, 53, 54, 55 .int 56, 57, 58, 59, 60, 61, 62, 63 .int 64, 65, 66, 67, 68, 69, 70, 71 - .int 72, 73, 74, 75, 76, 77, 79, 79 + .int 72, 73, 74, 75, 76, 77, 78, 79 .int 80, 81, 82, 83, 84, 85, 86, 87 .int 88, 89, 90, 91, 92, 93, 94, 95 .int 96, 97, 98, 99, 100, 101, 102, 103 @@ -458,7 +458,7 @@ RVMODEL_DATA_BEGIN .fill 28, 4, 0xdeadbeef # this is annoying, but RVMODEL_DATA_END and BEGIN insert # 4 bytes. This needs to be aligned to a cacheline -.align 6 + .align 6 Destination1: .fill 128, 4, 0xdeadbeef Destination2: @@ -469,7 +469,7 @@ Destination4: .fill 128, 4, 0xdeadbeef signature: - .fill 128, 4, 0xdeadbeef + .fill 32, 4, 0x0bad0bad RVMODEL_DATA_END From 310b700550aee635f0bf3fdda58601f73e064ff5 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 21 Aug 2023 13:46:09 -0500 Subject: [PATCH 21/24] Have a working 32 bit cbom test! --- sim/wave.do | 669 +++++++++--------- testbench/tests.vh | 1 + .../rv32i_m/privilege/Makefrag | 1 + .../references/WALLY-cbom-01.reference_output | 128 ---- .../rv64i_m/privilege/src/WALLY-cbom-01.S | 3 - 5 files changed, 352 insertions(+), 450 deletions(-) diff --git a/sim/wave.do b/sim/wave.do index ffad5c84a..6fd560251 100644 --- a/sim/wave.do +++ b/sim/wave.do @@ -11,14 +11,15 @@ add wave -noupdate /testbench/FunctionName/FunctionName/FunctionAddr add wave -noupdate /testbench/FunctionName/FunctionName/ProgramAddrIndex add wave -noupdate /testbench/FunctionName/FunctionName/FunctionName add wave -noupdate /testbench/FunctionName/FunctionName/ProgramAddrMapLineCount -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/RetM -add wave -noupdate -expand -group HDU -group hazards -color Pink /testbench/dut/core/hzu/TrapM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/LoadStallD -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/ifu/IFUStallF -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/LSUStallM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/MDUStallD -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/DivBusyE -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/FDivBusyE +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM +add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/BPWrongE +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/MDUStallD +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM @@ -177,200 +178,216 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK -add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW -add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM -add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM -add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM -add wave -noupdate -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM -add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM -add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall -add wave -noupdate -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB -add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW -add wave -noupdate -group lsu -group bus /testbench/dut/core/ebu/ebu/HCLK -add wave -noupdate -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUHWDATA -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck -add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW -add wave -noupdate -group lsu -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState -add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr -add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrE -add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet -add wave -noupdate -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} -add wave -noupdate -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay -add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn -add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CacheSet -add wave -noupdate -group lsu -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} -add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU -add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU -add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay -add wave -noupdate -group lsu -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate -add wave -noupdate -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate -add wave -noupdate -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded -add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty -add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr -add wave -noupdate -group lsu -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr -add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag -add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn -add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn -add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag -add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush -add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay -add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr -add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr -add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet -add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU -add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU -add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn -add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine -add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr -add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay -add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay -add wave -noupdate -group lsu -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} -add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM[62]} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet -add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} -add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextSet -add wave -noupdate -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr -add wave -noupdate -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck -add wave -noupdate -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord -add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk -add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE -add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF -add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF -add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/DCacheStallM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM +add wave -noupdate -expand -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/FWriteDataM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/ebu/ebu/HCLK +add wave -noupdate -expand -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/BusStall +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUHWDATA +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOp +add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet +add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelFlush +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelWriteback +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/TagWay +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/Tag +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CacheSet +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM[62]} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ClearValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ClearValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ClearValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/TagWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/TagWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/TagWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/TagWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextSet +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusRW +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite +add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress +add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions +add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable +add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent +add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault +add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF +add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM +add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk +add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/DCacheStallM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/MExtInt @@ -437,121 +454,131 @@ add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/du add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/core/FlushW add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/PCM add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM -add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/InstrRawF -add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF -add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUStallF -add wave -noupdate -expand -group ifu -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState -add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/SpillF -add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallF -add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissF -add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF -add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE -add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST -add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS -add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE -add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR -add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush -add wave -noupdate -expand -group ifu -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState -add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HRDATA -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/FlushStage -add wave -noupdate -expand -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheRW -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheAccess -add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay -add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF -add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr -add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay -add wave -noupdate -expand -group ifu -expand -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/SelectedWriteWordEn} -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/SelectedWriteWordEn} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/SelectedWriteWordEn} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/SelectedWriteWordEn} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite -add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF -add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/VAdr -add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress -add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/Matches -add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/InstrPageFaultF -add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/TLBFlush -add wave -noupdate -expand -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Valid} -add wave -noupdate -expand -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/PageType} -add wave -noupdate -expand -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key} -add wave -noupdate -expand -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key0} -add wave -noupdate -expand -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key1} -add wave -noupdate -expand -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query0} -add wave -noupdate -expand -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query1} -add wave -noupdate -expand -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Valid} -add wave -noupdate -expand -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageTypeWriteVal} -add wave -noupdate -expand -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageType} -add wave -noupdate -expand -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key} -add wave -noupdate -expand -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key0} -add wave -noupdate -expand -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1} -add wave -noupdate -expand -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0} -add wave -noupdate -expand -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1} -add wave -noupdate -expand -group {Performance Counters} -label MCYCLE -radix hexadecimal {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]} -add wave -noupdate -expand -group {Performance Counters} -label MINSTRET -radix hexadecimal {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]} -add wave -noupdate -expand -group {Performance Counters} -group BP -label Branch -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]} -add wave -noupdate -expand -group {Performance Counters} -group BP -label {BP Dir Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]} -add wave -noupdate -expand -group {Performance Counters} -group BP -label {Jump (Not Return)} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]} -add wave -noupdate -expand -group {Performance Counters} -group BP -label Return -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]} -add wave -noupdate -expand -group {Performance Counters} -group BP -label {BP Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]} -add wave -noupdate -expand -group {Performance Counters} -group BP -label {BTA Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]} -add wave -noupdate -expand -group {Performance Counters} -group BP -label {RAS Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]} -add wave -noupdate -expand -group {Performance Counters} -group BP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]} -add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {I Cache Access} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[16]} -add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {I Cache Miss} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[17]} -add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {I Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[18]} -add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {Load Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]} -add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {Store Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]} -add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]} -add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]} -add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {D Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]} -add wave -noupdate -expand -group {Performance Counters} -group Privileged -label {CSR Write} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[19]} -add wave -noupdate -expand -group {Performance Counters} -group Privileged -label Fence.I {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[20]} -add wave -noupdate -expand -group {Performance Counters} -group Privileged -label sfence.VMA {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[21]} -add wave -noupdate -expand -group {Performance Counters} -group Privileged -label Interrupt {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[22]} -add wave -noupdate -expand -group {Performance Counters} -group Privileged -label Exception {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[23]} -add wave -noupdate -expand -group {Performance Counters} -label {FDiv or IDiv Cycles} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[24]} -add wave -noupdate -expand -group {Performance Counters} /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW +add wave -noupdate -group ifu /testbench/dut/core/ifu/InstrRawF +add wave -noupdate -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF +add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUStallF +add wave -noupdate -group ifu -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState +add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/SpillF +add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallF +add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissF +add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush +add wave -noupdate -group ifu -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HRDATA +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/FlushStage +add wave -noupdate -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheRW +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheAccess +add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay +add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF +add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr +add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay +add wave -noupdate -group ifu -expand -group icache -color Gold -radix unsigned /testbench/dut/core/ifu/bus/icache/icache/CacheSet +add wave -noupdate -group ifu -expand -group icache -expand -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/SelectedWriteWordEn} +add wave -noupdate -group ifu -expand -group icache -expand -group way3 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/CacheTagMem/RAM} +add wave -noupdate -group ifu -expand -group icache -expand -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/ValidBits} +add wave -noupdate -group ifu -expand -group icache -expand -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -expand -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -expand -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -expand -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -expand -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -expand -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -expand -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -expand -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -expand -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/SelectedWriteWordEn} +add wave -noupdate -group ifu -expand -group icache -expand -group way2 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/CacheTagMem/RAM} +add wave -noupdate -group ifu -expand -group icache -expand -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/ValidBits} +add wave -noupdate -group ifu -expand -group icache -expand -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -expand -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -expand -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -expand -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -expand -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -expand -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -expand -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -expand -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -expand -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/HitWay} +add wave -noupdate -group ifu -expand -group icache -expand -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/SelectedWriteWordEn} +add wave -noupdate -group ifu -expand -group icache -expand -group way1 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/CacheTagMem/RAM} +add wave -noupdate -group ifu -expand -group icache -expand -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/ValidBits} +add wave -noupdate -group ifu -expand -group icache -expand -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -expand -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -expand -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -expand -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -expand -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -expand -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -expand -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -expand -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -expand -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/SelectedWriteWordEn} +add wave -noupdate -group ifu -expand -group icache -expand -group way0 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/CacheTagMem/RAM} +add wave -noupdate -group ifu -expand -group icache -expand -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/ValidBits} +add wave -noupdate -group ifu -expand -group icache -expand -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -expand -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -expand -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -expand -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -expand -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -expand -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -expand -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -expand -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/VAdr +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/Matches +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/InstrPageFaultF +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/TLBFlush +add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Valid} +add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/PageType} +add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key} +add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key0} +add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key1} +add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query0} +add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query1} +add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Valid} +add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageTypeWriteVal} +add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageType} +add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key} +add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key0} +add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1} +add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0} +add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1} +add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]} +add wave -noupdate -group {Performance Counters} -label MINSTRET -radix hexadecimal {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]} +add wave -noupdate -group {Performance Counters} -group BP -label Branch -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]} +add wave -noupdate -group {Performance Counters} -group BP -label {BP Dir Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]} +add wave -noupdate -group {Performance Counters} -group BP -label {Jump (Not Return)} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]} +add wave -noupdate -group {Performance Counters} -group BP -label Return -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]} +add wave -noupdate -group {Performance Counters} -group BP -label {BP Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]} +add wave -noupdate -group {Performance Counters} -group BP -label {BTA Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]} +add wave -noupdate -group {Performance Counters} -group BP -label {RAS Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]} +add wave -noupdate -group {Performance Counters} -group BP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]} +add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {I Cache Access} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[16]} +add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {I Cache Miss} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[17]} +add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {I Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[18]} +add wave -noupdate -group {Performance Counters} -group DCACHE -label {Load Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]} +add wave -noupdate -group {Performance Counters} -group DCACHE -label {Store Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]} +add wave -noupdate -group {Performance Counters} -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]} +add wave -noupdate -group {Performance Counters} -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]} +add wave -noupdate -group {Performance Counters} -group DCACHE -label {D Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]} +add wave -noupdate -group {Performance Counters} -group Privileged -label {CSR Write} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[19]} +add wave -noupdate -group {Performance Counters} -group Privileged -label Fence.I {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[20]} +add wave -noupdate -group {Performance Counters} -group Privileged -label sfence.VMA {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[21]} +add wave -noupdate -group {Performance Counters} -group Privileged -label Interrupt {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[22]} +add wave -noupdate -group {Performance Counters} -group Privileged -label Exception {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[23]} +add wave -noupdate -group {Performance Counters} -label {FDiv or IDiv Cycles} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[24]} +add wave -noupdate -group {Performance Counters} /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW add wave -noupdate -group {ifu } -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/HREADY add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/FetchBuffer @@ -614,8 +641,12 @@ add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/Stall add wave -noupdate /testbench/loggers/ICacheLogger/Enable add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/CacheEn +add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/LRUWriteEn +add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/FlushStage +add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/CacheEn +add wave -noupdate /testbench/dut/core/ifu/CacheableF TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {746867 ns} 1} {{Cursor 4} {698066 ns} 0} +WaveRestoreCursors {{Cursor 4} {172636 ns} 1} {{Cursor 4} {152124 ns} 0} {{Cursor 3} {152766 ns} 1} quietly wave cursor active 2 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -631,4 +662,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {697650 ns} {698666 ns} +WaveRestoreZoom {152015 ns} {152227 ns} diff --git a/testbench/tests.vh b/testbench/tests.vh index 06c4cbe5a..494a41cf5 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -2029,6 +2029,7 @@ string arch64zbs[] = '{ `WALLYTEST, "rv32i_m/privilege/src/WALLY-csr-permission-s-01.S", "rv32i_m/privilege/src/WALLY-csr-permission-u-01.S", + "rv32i_m/privilege/src/WALLY-cbom-01.S", "rv32i_m/privilege/src/WALLY-mie-01.S", "rv32i_m/privilege/src/WALLY-minfo-01.S", "rv32i_m/privilege/src/WALLY-misa-01.S", diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag index 23806cf67..472157f0d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag @@ -57,6 +57,7 @@ target_tests_nosim = \ WALLY-clint-01 \ WALLY-plic-01 \ WALLY-uart-01 \ + WALLY-cbom-01 \ rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests)) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-cbom-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-cbom-01.reference_output index a44010745..9dd00bf9b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-cbom-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-cbom-01.reference_output @@ -410,134 +410,6 @@ deadbeef 0000007d 0000007e 0000007f -deadbeef # destination 4 -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef ffffffff # signature The test writes -1 for correct answers and the a positive integer for incorrect copies. ffffffff ffffffff diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S index 374ee1c88..4a45ec676 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S @@ -465,9 +465,6 @@ Destination2: .fill 128, 4, 0xdeadbeef Destination3: .fill 128, 4, 0xdeadbeef -Destination4: - .fill 128, 4, 0xdeadbeef - signature: .fill 32, 4, 0x0bad0bad From 0662df511d45c9222797ecbce6e3222c51fc0177 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 21 Aug 2023 13:48:20 -0500 Subject: [PATCH 22/24] Modified rv32gc and rv64gc configs to enabled Zicbom. --- config/rv32gc/config.vh | 2 +- config/rv64gc/config.vh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index 5479e5fde..b08bf06d8 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -45,7 +45,7 @@ localparam ZICNTR_SUPPORTED = 1; localparam ZIHPM_SUPPORTED = 1; localparam ZFH_SUPPORTED = 0; localparam SSTC_SUPPORTED = 1; -localparam ZICBOM_SUPPORTED = 0; +localparam ZICBOM_SUPPORTED = 1; localparam ZICBOZ_SUPPORTED = 0; localparam ZICBOP_SUPPORTED = 0; localparam SVPBMT_SUPPORTED = 0; diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index 31336c6b8..939ce72c8 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -47,7 +47,7 @@ localparam ZICNTR_SUPPORTED = 1; localparam ZIHPM_SUPPORTED = 1; localparam ZFH_SUPPORTED = 0; localparam SSTC_SUPPORTED = 1; -localparam ZICBOM_SUPPORTED = 0; +localparam ZICBOM_SUPPORTED = 1; localparam ZICBOZ_SUPPORTED = 0; localparam ZICBOP_SUPPORTED = 0; localparam SVPBMT_SUPPORTED = 0; From 1e0f1aeeac3f06b2fabff03717758662376e7950 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 21 Aug 2023 14:35:42 -0500 Subject: [PATCH 23/24] Updated artyA7 debugger to match book. --- fpga/constraints/marked_debug_all.txt | 131 ++++++++++++++++++++++++ fpga/constraints/marked_debug_small.txt | 7 ++ fpga/constraints/small-debug.xdc | 12 +-- 3 files changed, 144 insertions(+), 6 deletions(-) create mode 100644 fpga/constraints/marked_debug_all.txt create mode 100644 fpga/constraints/marked_debug_small.txt diff --git a/fpga/constraints/marked_debug_all.txt b/fpga/constraints/marked_debug_all.txt new file mode 100644 index 000000000..3973fc451 --- /dev/null +++ b/fpga/constraints/marked_debug_all.txt @@ -0,0 +1,131 @@ +lsu/lsu.sv: logic IEUAdrM +lsu/lsu.sv: logic WriteDataM +lsu/lsu.sv: logic LSUHADDR +lsu/lsu.sv: logic HRDATA +lsu/lsu.sv: logic LSUHWDATA +lsu/lsu.sv: logic LSUHREADY +lsu/lsu.sv: logic LSUHWRITE +lsu/lsu.sv: logic LSUHSIZE +lsu/lsu.sv: logic LSUHBURST +lsu/lsu.sv: logic LSUHTRANS +lsu/lsu.sv: logic LSUHWSTRB +lsu/lsu.sv: logic IHAdrM +ieu/regfile.sv: logic rf +ieu/datapath.sv: logic RegWriteW +hazard/hazard.sv: logic BPPredWrongE +hazard/hazard.sv: logic LoadStallD +hazard/hazard.sv: logic FCvtIntStallD +hazard/hazard.sv: logic DivBusyE +hazard/hazard.sv: logic EcallFaultM +hazard/hazard.sv: logic WFIStallM +hazard/hazard.sv: logic StallF +hazard/hazard.sv: logic FlushD +cache/cachefsm.sv: statetype CurrState +wally/wallypipelinedcore.sv: logic TrapM +wally/wallypipelinedcore.sv: logic SrcAM +wally/wallypipelinedcore.sv: logic InstrM +wally/wallypipelinedcore.sv: logic PCM +wally/wallypipelinedcore.sv: logic MemRWM +wally/wallypipelinedcore.sv: logic InstrValidM +wally/wallypipelinedcore.sv: logic WriteDataM +wally/wallypipelinedcore.sv: logic IEUAdrM +wally/wallypipelinedcore.sv: logic HRDATA +ifu/spill.sv: statetype CurrState +ifu/ifu.sv: logic IFUStallF +ifu/ifu.sv: logic IFUHADDR +ifu/ifu.sv: logic HRDATA +ifu/ifu.sv: logic IFUHREADY +ifu/ifu.sv: logic IFUHWRITE +ifu/ifu.sv: logic IFUHSIZE +ifu/ifu.sv: logic IFUHBURST +ifu/ifu.sv: logic IFUHTRANS +ifu/ifu.sv: logic PCF +ifu/ifu.sv: logic PCNextF +ifu/ifu.sv: logic PCPF +ifu/ifu.sv: logic PostSpillInstrRawF +mmu/hptw.sv: logic ITLBWriteF +mmu/hptw.sv: statetype WalkerState +privileged/csrs.sv: logic CSRSReadValM +privileged/csrs.sv: logic SEPC_REGW +privileged/csrs.sv: logic MIP_REGW +privileged/csrs.sv: logic SSCRATCH_REGW +privileged/csrs.sv: logic SCAUSE_REGW +privileged/csr.sv: logic CSRReadValM +privileged/csr.sv: logic CSRSrcM +privileged/csr.sv: logic CSRWriteValM +privileged/csr.sv: logic MSTATUS_REGW +privileged/trap.sv: logic InstrMisalignedFaultM +privileged/trap.sv: logic BreakpointFaultM +privileged/trap.sv: logic LoadAccessFaultM +privileged/trap.sv: logic LoadPageFaultM +privileged/trap.sv: logic mretM +privileged/trap.sv: logic MIP_REGW +privileged/trap.sv: logic PendingIntsM +privileged/privileged.sv: logic CSRReadM +privileged/privileged.sv: logic InterruptM +privileged/csrc.sv: logic HPMCOUNTER_REGW +privileged/csri.sv: logic MExtInt +privileged/csri.sv: logic MIP_REGW_writeabl +privileged/csrm.sv: logic MIP_REGW +privileged/csrm.sv: logic MEPC_REGW +privileged/csrm.sv: logic MEDELEG_REGW +privileged/csrm.sv: logic MIDELEG_REGW +privileged/csrm.sv: logic MSCRATCH_REGW +privileged/csrm.sv: logic MCAUSE_REGW +uncore/uart_apb.sv: logic SIN +uncore/uart_apb.sv: logic SOUT +uncore/uart_apb.sv: logic OUT1b +uncore/uartPC16550D.sv: logic RBR +uncore/uartPC16550D.sv: logic FCR +uncore/uartPC16550D.sv: logic IER +uncore/uartPC16550D.sv: logic MCR +uncore/uartPC16550D.sv: logic baudpulse +uncore/uartPC16550D.sv: statetype rxstate +uncore/uartPC16550D.sv: logic rxfifo +uncore/uartPC16550D.sv: logic txfifo +uncore/uartPC16550D.sv: logic rxfifohead +uncore/uartPC16550D.sv: logic rxfifoentries +uncore/uartPC16550D.sv: logic RXBR +uncore/uartPC16550D.sv: logic rxtimeoutcnt +uncore/uartPC16550D.sv: logic rxparityerr +uncore/uartPC16550D.sv: logic rxdataready +uncore/uartPC16550D.sv: logic rxfifoempty +uncore/uartPC16550D.sv: logic rxdata +uncore/uartPC16550D.sv: logic RXerrbit +uncore/uartPC16550D.sv: logic rxfullbitunwrapped +uncore/uartPC16550D.sv: logic txdata +uncore/uartPC16550D.sv: logic txnextbit +uncore/uartPC16550D.sv: logic txfifoempty +uncore/uartPC16550D.sv: logic fifoenabled +uncore/uartPC16550D.sv: logic RXerr +uncore/uartPC16550D.sv: logic THRE +uncore/uartPC16550D.sv: logic rxdataavailintr +uncore/uartPC16550D.sv: logic intrID +uncore/uncore.sv: logic HSELEXTSDCD +uncore/plic_apb.sv: logic MExtInt +uncore/plic_apb.sv: logic Din +uncore/plic_apb.sv: logic requests +uncore/plic_apb.sv: logic intPriority +uncore/plic_apb.sv: logic intInProgress +uncore/plic_apb.sv: logic intThreshold +uncore/plic_apb.sv: logic intEn +uncore/plic_apb.sv: logic intClaim +uncore/plic_apb.sv: logic irqMatrix +uncore/plic_apb.sv: logic priorities_with_irqs +uncore/plic_apb.sv: logic max_priority_with_irqs +uncore/plic_apb.sv: logic irqs_at_max_priority +uncore/plic_apb.sv: logic threshMask +uncore/clint_apb.sv: logic MTIME +uncore/clint_apb.sv: logic MTIMECMP +ebu/ebu.sv: logic HCLK +ebu/ebu.sv: logic HREADY +ebu/ebu.sv: logic HRESP +ebu/ebu.sv: logic HADDR +ebu/ebu.sv: logic HWRITE +ebu/ebu.sv: logic HSIZE +ebu/ebu.sv: logic HBURST +ebu/ebu.sv: logic HPROT +ebu/ebu.sv: logic HTRANS +ebu/ebu.sv: logic HMASTLOC +ebu/buscachefsm.sv: busstatetype CurrState +ebu/busfsm.sv: busstatetype CurrState diff --git a/fpga/constraints/marked_debug_small.txt b/fpga/constraints/marked_debug_small.txt new file mode 100644 index 000000000..1d23c29a2 --- /dev/null +++ b/fpga/constraints/marked_debug_small.txt @@ -0,0 +1,7 @@ +wally/wallypipelinedcore.sv: logic PCM +wally/wallypipelinedcore.sv: logic TrapM +wally/wallypipelinedcore.sv: logic InstrValidM +wally/wallypipelinedcore.sv: logic InstrM +lsu/lsu.sv: logic IEUAdrM +lsu/lsu.sv: logic MemRWM +mmu/hptw.sv: logic SATP_REGW diff --git a/fpga/constraints/small-debug.xdc b/fpga/constraints/small-debug.xdc index 28b7e69d5..7bf498a79 100644 --- a/fpga/constraints/small-debug.xdc +++ b/fpga/constraints/small-debug.xdc @@ -39,19 +39,19 @@ set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 32 [get_debug_ports u_ila_0/probe4] +set_property port_width 2 [get_debug_ports u_ila_0/probe4] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] -connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]] +connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/MemRWM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/MemRWM[1]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe5] +set_property port_width 64 [get_debug_ports u_ila_0/probe5] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] -connect_debug_port u_ila_0/probe5 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHREADY ]] +connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/IEUAdrM[63]} ]] create_debug_port u_ila_0 probe -set_property port_width 64 [get_debug_ports u_ila_0/probe6] +set_property port_width 48 [get_debug_ports u_ila_0/probe6] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] -connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]] +connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[63]}]] # the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock. #connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk] From a16cde3dc665b0f3385d8153b178701281dcffce Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 21 Aug 2023 15:12:59 -0500 Subject: [PATCH 24/24] Removed unused file. --- fpga/constraints/test.file | 1 - 1 file changed, 1 deletion(-) delete mode 100644 fpga/constraints/test.file diff --git a/fpga/constraints/test.file b/fpga/constraints/test.file deleted file mode 100644 index ea8c7d25a..000000000 --- a/fpga/constraints/test.file +++ /dev/null @@ -1 +0,0 @@ -test to make sure i can still merge my code into the new open hardware group.