diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 7c61d4682..42596464c 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -22,13 +22,13 @@ add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DataStall -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/DataStall +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE @@ -57,6 +57,7 @@ add wave -noupdate -group Bpred -group BTB -divider Lookup add wave -noupdate -group Bpred -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/TargetPC add wave -noupdate -group Bpred -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/Valid add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/BPPredWrongE +add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM @@ -88,26 +89,33 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags -add wave -noupdate -group alu -divider internals -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu -add wave -noupdate /testbench/InstrFName +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/result +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/flags +add wave -noupdate -expand -group alu -divider internals +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/overflow +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/carry +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu add wave -noupdate -expand -group {dcache memory} /testbench/dut/hart/dmem/MemReadM add wave -noupdate -expand -group {dcache memory} /testbench/dut/hart/dmem/MemWriteM add wave -noupdate -expand -group {dcache memory} /testbench/dut/hart/dmem/MemAckW -add wave -noupdate -group dcache /testbench/dut/hart/MemAdrM -add wave -noupdate -group dcache /testbench/dut/hart/MemPAdrM -add wave -noupdate -group dcache /testbench/dut/hart/WriteDataM -add wave -noupdate -group dcache /testbench/dut/hart/dmem/MemRWM +add wave -noupdate -expand -group dcache -expand -group {cpu request} /testbench/dut/hart/dmem/MemRWM +add wave -noupdate -expand -group dcache -expand -group {cpu request} /testbench/dut/hart/dmem/AtomicM +add wave -noupdate -expand -group dcache -expand -group {cpu request} /testbench/dut/hart/MemAdrM +add wave -noupdate -expand -group dcache -expand -group {cpu request} /testbench/dut/hart/dmem/ReadDataW +add wave -noupdate -expand -group dcache -expand -group {cpu request} /testbench/dut/hart/WriteDataM +add wave -noupdate -expand -group dcache -color Gray90 /testbench/dut/hart/dmem/CurrState +add wave -noupdate -expand -group dcache /testbench/dut/hart/MemPAdrM +add wave -noupdate -expand -group dcache /testbench/dut/hart/dmem/MemAccessM +add wave -noupdate -expand -group dcache /testbench/dut/hart/dmem/AtomicMaskedM +add wave -noupdate -expand -group dcache /testbench/dut/hart/dmem/MemAckW +add wave -noupdate -expand -group dcache /testbench/dut/hart/dmem/genblk1/lrM +add wave -noupdate -expand -group dcache /testbench/dut/hart/dmem/genblk1/scM add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E @@ -231,8 +239,9 @@ add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HMASTLOCK add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HADDRD add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HSIZED add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HWRITED +add wave -noupdate /testbench/dut/hart/dmem/genblk1/scM TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {9808206 ns} 0} {{Cursor 3} {9807791 ns} 0} {{Cursor 4} {85 ns} 0} +WaveRestoreCursors {{Cursor 2} {12215488 ns} 0} {{Cursor 4} {12211487 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 513 @@ -248,4 +257,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {0 ns} {1829700 ns} +WaveRestoreZoom {12215315 ns} {12215675 ns} diff --git a/wally-pipelined/src/dmem/dmem.sv b/wally-pipelined/src/dmem/dmem.sv index 16813629c..d8dad8bb8 100644 --- a/wally-pipelined/src/dmem/dmem.sv +++ b/wally-pipelined/src/dmem/dmem.sv @@ -27,6 +27,7 @@ `include "wally-config.vh" +// *** Ross Thompson amo misalignment check? module dmem ( input logic clk, reset, input logic StallW, FlushW, @@ -40,6 +41,7 @@ module dmem ( input logic [1:0] AtomicM, output logic [`XLEN-1:0] MemPAdrM, output logic MemReadM, MemWriteM, + output logic [1:0] AtomicMaskedM, output logic DataMisalignedM, // Writeback Stage input logic MemAckW, @@ -68,8 +70,8 @@ module dmem ( localparam STATE_READY = 0; localparam STATE_FETCH = 1; - localparam STATE_STALLED = 2; - + localparam STATE_FETCH_AMO = 2; + localparam STATE_STALLED = 3; tlb #(.ENTRY_BITS(3), .ITLB(0)) dtlb(.TLBAccessType(MemRWM), .VirtualAddress(MemAdrM), .PageTableEntryWrite(PageTableEntryM), .PageTypeWrite(PageTypeM), @@ -95,6 +97,7 @@ module dmem ( // *** this is also the place to squash if the cache is hit assign MemReadM = MemRWM[1] & ~DataMisalignedM & CurrState != STATE_STALLED; assign MemWriteM = MemRWM[0] & ~DataMisalignedM && ~SquashSCM & CurrState != STATE_STALLED; + assign AtomicMaskedM = CurrState != STATE_STALLED ? AtomicM : 2'b00 ; assign MemAccessM = |MemRWM; // Determine if address is valid @@ -143,8 +146,11 @@ module dmem ( always_comb begin case (CurrState) - STATE_READY: if (MemAccessM & ~DataMisalignedM) NextState = STATE_FETCH; - else NextState = STATE_READY; + STATE_READY: if (MemRWM[1] & MemRWM[0]) NextState = STATE_FETCH_AMO; // *** should be some misalign check + else if (MemAccessM & ~DataMisalignedM) NextState = STATE_FETCH; + else NextState = STATE_READY; + STATE_FETCH_AMO: if (MemAckW) NextState = STATE_FETCH; + else NextState = STATE_FETCH_AMO; STATE_FETCH: if (MemAckW & ~StallW) NextState = STATE_READY; else if (MemAckW & StallW) NextState = STATE_STALLED; else NextState = STATE_FETCH; diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv index b14e7bcbe..31b9e9c67 100644 --- a/wally-pipelined/src/ebu/ahblite.sv +++ b/wally-pipelined/src/ebu/ahblite.sv @@ -39,7 +39,7 @@ module ahblite ( input logic StallW, FlushW, // Load control input logic UnsignedLoadM, - input logic [1:0] AtomicM, + input logic [1:0] AtomicMaskedM, input logic [6:0] Funct7M, // Signals from Instruction Cache input logic [`XLEN-1:0] InstrPAdrF, // *** rename these to match block diagram @@ -114,7 +114,7 @@ module ahblite ( always_comb case (BusState) IDLE: if (MMUTranslate) NextBusState = MMUTRANSLATE; - else if (AtomicM[1]) NextBusState = ATOMICREAD; + else if (AtomicMaskedM[1]) NextBusState = ATOMICREAD; else if (MemReadM) NextBusState = MEMREAD; // Memory has priority over instructions else if (MemWriteM) NextBusState = MEMWRITE; else if (InstrReadF) NextBusState = INSTRREAD; @@ -188,7 +188,8 @@ module ahblite ( assign InstrRData = HRDATA; assign InstrAckF = (BusState == INSTRREAD) && (NextBusState != INSTRREAD) || (BusState == INSTRREADC) && (NextBusState != INSTRREADC); - assign MemAckW = (BusState == MEMREAD) && (NextBusState != MEMREAD) || (BusState == MEMWRITE) && (NextBusState != MEMWRITE); + assign MemAckW = (BusState == MEMREAD) && (NextBusState != MEMREAD) || (BusState == MEMWRITE) && (NextBusState != MEMWRITE) || + ((BusState == ATOMICREAD) && (NextBusState != ATOMICREAD)) || ((BusState == ATOMICWRITE) && (NextBusState != ATOMICWRITE)); assign MMUReadPTE = HRDATA; assign ReadDataM = HRDATAMasked; // changed from W to M dh 2/7/2021 assign CaptureDataM = ((BusState == MEMREAD) && (NextBusState != MEMREAD)) || @@ -199,6 +200,7 @@ module ahblite ( flopenr #(`XLEN) ReadDataNewWReg(clk, reset, CaptureDataM, ReadDataM, ReadDataNewW); flopenr #(`XLEN) ReadDataOldWReg(clk, reset, CaptureDataM, ReadDataNewW, ReadDataOldW); assign ReadDataW = (BusState == INSTRREADC) ? ReadDataOldW : ReadDataNewW; + //assign ReadDataW = (BusState == INSTRREADC) ? ReadDataOldW : ReadDataNewW; // Extract and sign-extend subwords if necessary subwordread swr(.*); @@ -211,7 +213,7 @@ module ahblite ( // .result(AMOResult)); amoalu amoalu(.srca(ReadDataW), .srcb(WriteDataM), .funct(Funct7M), .width(MemSizeM), .result(AMOResult)); - mux2 #(`XLEN) wdmux(WriteDataM, AMOResult, AtomicM[1], WriteData); + mux2 #(`XLEN) wdmux(WriteDataM, AMOResult, AtomicMaskedM[1], WriteData); end else assign WriteData = WriteDataM; endgenerate diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 69275e9c7..5526976a0 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -124,6 +124,7 @@ module wallypipelinedhart ( // bus interface to dmem logic MemReadM, MemWriteM; + logic [1:0] AtomicMaskedM; logic [2:0] Funct3M; logic [`XLEN-1:0] MemAdrM, MemPAdrM, WriteDataM; logic [`XLEN-1:0] ReadDataW;