From d7ef490c125c385130b8f0dab6a22142122e8289 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 27 Nov 2023 01:27:09 -0600 Subject: [PATCH] Sutble bug in the cacheway logic for cacheline invalidation. --- src/cache/cacheway.sv | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 9fb836e93..67f4f5a74 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -68,7 +68,7 @@ module cacheway import cvw::*; #(parameter cvw_t P, logic SelTag; logic SelectedWriteWordEn; logic [LINELEN/8-1:0] FinalByteMask; - logic SetValidEN; + logic SetValidEN, ClearValidEN; logic SetValidWay; logic ClearValidWay; logic SetDirtyWay; @@ -102,6 +102,7 @@ module cacheway import cvw::*; #(parameter cvw_t P, assign ClearDirtyWay = ClearDirty & SelData; assign SelectedWriteWordEn = (SetValidWay | SetDirtyWay) & ~FlushStage; // exclusion-tag: icache SelectedWiteWordEn assign SetValidEN = SetValidWay & ~FlushStage; // exclusion-tag: cache SetValidEN + assign ClearValidEN = ClearValidWay & ~FlushStage; // exclusion-tag: cache SetValidEN // If writing the whole line set all write enables to 1, else only set the correct word. assign FinalByteMask = SetValidWay ? '1 : LineByteMask; // OR @@ -156,7 +157,8 @@ module cacheway import cvw::*; #(parameter cvw_t P, if(CacheEn) begin ValidWay <= #1 ValidBits[CacheSet]; if(InvalidateCache) ValidBits <= #1 '0; // exclusion-tag: dcache invalidateway - else if (SetValidEN | (ClearValidWay & ~FlushStage)) ValidBits[CacheSet] <= #1 SetValidWay; + else if (SetValidEN) ValidBits[CacheSet] <= #1 SetValidWay; + else if (ClearValidEN) ValidBits[CacheSet] <= #1 '0; end end