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divsqrt working for floating point

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cturek 2022-07-20 02:04:20 +00:00
parent f75d1c2eef
commit d7e90a7086
1 changed files with 1 additions and 1 deletions
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pipelined/srt/srt.sv
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@ -311,7 +311,7 @@ module creg(input logic clk,
);
logic [`DIVLEN+3:0] CMux;
mux2 #(`DIVLEN+4) Cmux({1'b1, C[`DIVLEN+3:1]}, {4'b1111, Sqrt, {(`DIVLEN-1){1'b0}}}, Start, CMux);
mux2 #(`DIVLEN+4) Cmux({1'b1, C[`DIVLEN+3:1]}, {4'b11111, Sqrt, {(`DIVLEN-1){1'b0}}}, Start, CMux);
flop #(`DIVLEN+4) cflop(clk, CMux, C);
endmodule