From d7df9c1054199bdce8afd85fb03c75c31b492042 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 29 Nov 2021 16:07:54 -0600 Subject: [PATCH] Fixed uart for FPGA config after merge. This still needs some work. --- wally-pipelined/src/uncore/uartPC16550D.sv | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/wally-pipelined/src/uncore/uartPC16550D.sv b/wally-pipelined/src/uncore/uartPC16550D.sv index 8ebf00d98..c6f3d5c15 100644 --- a/wally-pipelined/src/uncore/uartPC16550D.sv +++ b/wally-pipelined/src/uncore/uartPC16550D.sv @@ -137,23 +137,26 @@ module uartPC16550D( MCR <= #1 5'b0; LSR <= #1 8'b01100000; MSR <= #1 4'b0; - DLL <= #1 8'd1; // this cannot be zero with DLM also zer0. - DLM <= #1 8'b0; + if (`FPGA) begin + DLL <= #1 8'd11; + DLM <= #1 8'b0; + end else begin + DLL <= #1 8'd1; // this cannot be zero with DLM also zer0. + DLM <= #1 8'b0; + end /* -----\/----- EXCLUDED -----\/----- - DLL <= #1 8'd11; - DLM <= #1 8'b0; -----/\----- EXCLUDED -----/\----- */ SCR <= #1 8'b0; // not strictly necessary to reset end else begin if (~MEMWb) begin case (A) +/* -----\/----- EXCLUDED -----\/----- 3'b000: if (DLAB) DLL <= #1 Din; // else TXHR <= #1 Din; // TX handled in TX register/FIFO section 3'b001: if (DLAB) DLM <= #1 Din; else IER <= #1 Din[3:0]; - // *** BUG FIX ME for now for the divider to be 11. Our clock is 10 Mhz. 10Mhz /(11 * 16) = 56818 baud, which is close enough to 57600 baud -/* -----\/----- EXCLUDED -----\/----- - 3'b000: if (DLAB) DLL <= #1 8'd11 else TXHR <= #1 Din; // TX handled in TX register/FIFO section - 3'b001: if (DLAB) DLM <= #1 8'b0; else IER <= #1 Din[3:0]; -----/\----- EXCLUDED -----/\----- */ + // *** BUG FIX ME for now for the divider to be 11. Our clock is 10 Mhz. 10Mhz /(11 * 16) = 56818 baud, which is close enough to 57600 baud + 3'b000: if (DLAB) DLL <= #1 8'd11; //else TXHR <= #1 Din; // TX handled in TX register/FIFO section + 3'b001: if (DLAB) DLM <= #1 8'b0; else IER <= #1 Din[3:0]; 3'b010: FCR <= #1 {Din[7:6], 2'b0, Din[3], 2'b0, Din[0]}; // Write only FIFO Control Register; 4:5 reserved and 2:1 self-clearing 3'b011: LCR <= #1 Din;