fixt lint error

pipelined/src/fpu/fpu.sv

@@ -104,23 +104,27 @@ module fpu (
    logic 		  FOpCtrlQ;   
 
    // Fma Signals
-    logic [3*`NF+5:0]	SumE, SumM;                       
+   logic [3*`NF+5:0]	SumE, SumM;                       
-    logic [`NE+1:0]	    ProdExpE, ProdExpM;
+   logic [`NE+1:0]	    ProdExpE, ProdExpM;
-    logic 			    AddendStickyE, AddendStickyM;
+   logic 			    AddendStickyE, AddendStickyM;
-    logic 			    KillProdE, KillProdM;
+   logic 			    KillProdE, KillProdM;
-    logic 			    InvZE, InvZM;
+   logic 			    InvZE, InvZM;
-    logic 			    NegSumE, NegSumM;
+   logic 			    NegSumE, NegSumM;
-    logic 			    ZSgnEffE, ZSgnEffM;
+   logic 			    ZSgnEffE, ZSgnEffM;
-    logic 			    PSgnE, PSgnM;
+   logic 			    PSgnE, PSgnM;
-    logic [$clog2(3*`NF+7)-1:0]			FmaNormCntE, FmaNormCntM;
+   logic [$clog2(3*`NF+7)-1:0]			FmaNormCntE, FmaNormCntM;
 
    // Cvt Signals
-    logic [`NE:0]           CvtCalcExpE, CvtCalcExpM;    // the calculated expoent
+   logic [`NE:0]           CvtCalcExpE, CvtCalcExpM;    // the calculated expoent
-	 logic [`LOGCVTLEN-1:0]   CvtShiftAmtE, CvtShiftAmtM;  // how much to shift by
+   logic [`LOGCVTLEN-1:0]   CvtShiftAmtE, CvtShiftAmtM;  // how much to shift by
-    logic                   CvtResDenormUfE, CvtResDenormUfM;// does the result underflow or is denormalized
+   logic                   CvtResDenormUfE, CvtResDenormUfM;// does the result underflow or is denormalized
-    logic                   CvtResSgnE, CvtResSgnM;     // the result's sign
+   logic                   CvtResSgnE, CvtResSgnM;     // the result's sign
-    logic                   IntZeroE, IntZeroM;      // is the integer zero?
+   logic                   IntZeroE, IntZeroM;      // is the integer zero?
-    logic [`CVTLEN-1:0]      CvtLzcInE, CvtLzcInM;      // input to the Leading Zero Counter (priority encoder)
+   logic [`CVTLEN-1:0]      CvtLzcInE, CvtLzcInM;      // input to the Leading Zero Counter (priority encoder)
+   
+   //divide signals
+   logic [`DIVLEN-1:0] Quot;
+   logic [`NE:0] DivCalcExpM;
 
    // result and flag signals
    logic [63:0] 	  FDivResM, FDivResW;                 // divide/squareroot result
@@ -352,8 +356,8 @@ module fpu (
    assign FpLoadM = FResSelM[1];
 
    postprocess postprocess(.XSgnM, .YSgnM, .ZExpM, .XManM, .YManM, .ZManM, .FrmM, .FmtM, .ProdExpM, 
-                           .AddendStickyM, .KillProdM, .XZeroM, .YZeroM, .ZZeroM, .XInfM, .YInfM, 
+                           .AddendStickyM, .KillProdM, .XZeroM, .YZeroM, .ZZeroM, .XInfM, .YInfM, .Quot,
-                           .ZInfM, .XNaNM, .YNaNM, .ZNaNM, .XSNaNM, .YSNaNM, .ZSNaNM, .SumM, 
+                           .ZInfM, .XNaNM, .YNaNM, .ZNaNM, .XSNaNM, .YSNaNM, .ZSNaNM, .SumM, .DivCalcExpM,
                            .NegSumM, .InvZM, .ZDenormM, .ZSgnEffM, .PSgnM, .FOpCtrlM, .FmaNormCntM, 
                            .CvtCalcExpM, .CvtResDenormUfM,.CvtShiftAmtM, .CvtResSgnM, .FWriteIntM, 
                            .CvtLzcInM, .IntZeroM, .PostProcSelM, .PostProcResM, .PostProcFlgM, .FCvtIntResM);

pipelined/src/fpu/postprocess.sv

@@ -51,6 +51,7 @@ module postprocess(
     input logic [2:0]                       FOpCtrlM,       // choose which opperation (look below for values)
     input logic     [$clog2(3*`NF+7)-1:0]   FmaNormCntM,   // the normalization shift count
     input logic [`NE:0]           CvtCalcExpM,    // the calculated expoent
+    input logic [`NE:0]           DivCalcExpM,    // the calculated expoent
     input logic CvtResDenormUfM,
 	input logic [`LOGCVTLEN-1:0] CvtShiftAmtM,  // how much to shift by
     input logic                   CvtResSgnM,     // the result's sign
@@ -148,7 +149,7 @@ module postprocess(
                 ShiftIn =  {CvtShiftIn, {`NORMSHIFTSZ-`CVTLEN-`NF-1{1'b0}}};
             end
             2'b01: begin //div ***prob can take out
-                ShiftAmt = 1'b0;//{DivShiftAmt};
+                ShiftAmt = {$clog2(`NORMSHIFTSZ){1'b0}};//{DivShiftAmt};
                 ShiftIn =  {Quot, {`NORMSHIFTSZ-`DIVLEN{1'b0}}};
             end
             default: begin 
@@ -172,7 +173,7 @@ module postprocess(
     // round to infinity
     // round to nearest max magnitude
 
-    round round(.OutFmt, .FrmM, .Sticky, .AddendStickyM, .ZZeroM, .Plus1, .PostProcSelM, .CvtCalcExpM,
+    round round(.OutFmt, .FrmM, .Sticky, .AddendStickyM, .ZZeroM, .Plus1, .PostProcSelM, .CvtCalcExpM, .DivCalcExpM,
                 .InvZM, .RoundSgn, .SumExp, .FmaOp, .CvtOp, .CvtResDenormUfM, .CorrShifted, .ToInt,  .CvtResUf,
                 .UfPlus1, .FullResExp, .ResFrac, .ResExp, .Round, .RoundAdd, .UfLSBRes, .RoundExp);
 

pipelined/src/fpu/round.sv

@@ -23,6 +23,7 @@ module round(
     input logic  [`NE+1:0]      SumExp,         // exponent of the normalized sum
     input logic                 RoundSgn,      // the result's sign
     input logic [`NE:0]           CvtCalcExpM,    // the calculated expoent
+    input logic [`NE:0]           DivCalcExpM,    // the calculated expoent
     output logic                UfPlus1,  // do you add or subtract on from the result
     output logic [`NE+1:0]      FullResExp,      // ResExp with bits to determine sign and overflow
     output logic [`NF-1:0]      ResFrac,         // Result fraction
@@ -303,7 +304,7 @@ module round(
         case(PostProcSelM)
             2'b10: RoundExp = SumExp; // fma
             2'b00: RoundExp = {CvtCalcExpM[`NE], CvtCalcExpM}&{`NE+2{~CvtResDenormUfM|CvtResUf}}; // cvt
-            2'b01: RoundExp = 0; // divide
+            2'b01: RoundExp = {DivCalcExpM[`NE], DivCalcExpM[`NE:0]}; // divide
             default: RoundExp = 0; 
         endcase
 

pipelined/srt/srt-radix4.sv

@@ -43,13 +43,12 @@ module srtradix4 (
   output logic       DivDone,
   output logic [`DIVLEN-1:0] Quot,
   output logic [`XLEN-1:0] Rem, // *** later handle integers
-  output logic [`NE-1:0] DivExp
+  output logic [`NE:0] DivCalcExpE
 );
 
   // logic           qp, qz, qm; // quotient is +1, 0, or -1
   logic [3:0]     q;
-  logic [`NE-1:0] DivCalcExp;
+  logic [`NE:0] DivCalcExp;
-  logic           calcSign;
   logic [`DIVLEN-1:0]  X, Dpreproc;
   logic [`DIVLEN+3:0]  WS, WSA, WSN;
   logic [`DIVLEN+3:0]  WC, WCA, WCN;
@@ -87,7 +86,7 @@ module srtradix4 (
   qsel4 qsel4(.D, .WS, .WC, .q);
 
   // Store the expoenent and sign until division is DivDone
-  flopen #(`NE) expflop(clk, DivStart, DivCalcExp, DivExp);
+  flopen #(`NE+1) expflop(clk, DivStart, DivCalcExp, DivCalcExpE);
 
   // Divisor Selection logic
   // *** radix 4 change to choose -2 to 2
@@ -303,7 +302,7 @@ endmodule
 //////////////
 module expcalc(
   input logic  [`NE-1:0] XExpE, YExpE,
-  output logic [`NE-1:0] DivCalcExp
+  output logic [`NE:0] DivCalcExp
 );
 
   assign DivCalcExp = XExpE - YExpE + (`NE)'(`BIAS);

pipelined/testbench/testbench-fp.sv

@@ -70,7 +70,7 @@ module testbenchfp;
   logic 			          PSgnE;
   logic       DivSgn;
   logic [`DIVLEN-1:0] Quot;
-  logic [`NE-1:0] DivExp;
+  logic [`NE:0] DivCalcExp;
 
 
   ///////////////////////////////////////////////////////////////////////////////////////////////
@@ -643,7 +643,7 @@ module testbenchfp;
               .ProdExpE, .AddendStickyE, .KillProdE); 
               
   postprocess postprocess(.XSgnM(XSgn), .YSgnM(YSgn), .PostProcSelM(UnitVal[1:0]),
-              .ZExpM(ZExp),  .ZDenormM(ZDenorm), .FOpCtrlM(OpCtrlVal), .Quot,
+              .ZExpM(ZExp),  .ZDenormM(ZDenorm), .FOpCtrlM(OpCtrlVal), .Quot, .DivCalcExpM(DivCalcExp),
               .XManM(XMan), .YManM(YMan), .ZManM(ZMan), .CvtCalcExpM(CvtCalcExpE),
               .XNaNM(XNaN), .YNaNM(YNaN), .ZNaNM(ZNaN), .CvtResDenormUfM(CvtResDenormUfE),
               .XZeroM(XZero), .YZeroM(YZero), .ZZeroM(ZZero), .CvtShiftAmtM(CvtShiftAmtE),
@@ -659,7 +659,7 @@ module testbenchfp;
   fcmp fcmp   (.FmtE(ModFmt), .FOpCtrlE(OpCtrlVal), .XSgnE(XSgn), .YSgnE(YSgn), .XExpE(XExp), .YExpE(YExp), 
               .XManE(XMan), .YManE(YMan), .XZeroE(XZero), .YZeroE(YZero), .CmpIntResE(CmpRes),
               .XNaNE(XNaN), .YNaNE(YNaN), .XSNaNE(XSNaN), .YSNaNE(YSNaN), .FSrcXE(X), .FSrcYE(Y), .CmpNVE(CmpFlg[4]), .CmpFpResE(FpCmpRes));
-  srtradix4 srtradix4(.clk, .DivStart, .XExpE(XExp), .YExpE(YExp), .DivExp,
+  srtradix4 srtradix4(.clk, .DivStart, .XExpE(XExp), .YExpE(YExp), .DivCalcExpE(DivCalcExp),
                 .XFrac(XMan[`NF-1:0]), .YFrac(YMan[`NF-1:0]), .SrcA('0), .SrcB('0), .W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(OpCtrlVal[0]), 
                 .DivDone, .Quot, .Rem());