diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index a4b64fed6..fe685dc0e 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -41,7 +41,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( input logic InvalidateCacheM, input logic [11:0] NextAdr, // virtual address, but we only use the lower 12 bits. input logic [`PA_BITS-1:0] PAdr, // physical address - input logic [(`XLEN-1)/8:0] ByteWEN, + input logic [(`XLEN-1)/8:0] ByteWe, input logic [`XLEN-1:0] FinalWriteData, output logic CacheCommitted, output logic CacheStall, @@ -115,7 +115,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( // Array of cache ways, along with victim, hit, dirty, and read merging logic cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN) CacheWays[NUMWAYS-1:0]( - .clk, .reset, .RAdr, .PAdr, .CacheWriteData, .ByteWEN, + .clk, .reset, .RAdr, .PAdr, .CacheWriteData, .ByteWe, .SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay, .SelEvict, .VictimWay, .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .VictimDirtyWay, .VictimTagWay, .Invalidate(InvalidateCacheM)); diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index 30f42039d..fa3a0b68f 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -47,7 +47,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, input logic VictimWay, input logic FlushWay, input logic Invalidate, - input logic [(`XLEN-1)/8:0] ByteWEN, + input logic [(`XLEN-1)/8:0] ByteWe, output logic [LINELEN-1:0] ReadDataLineWay, output logic HitWay, @@ -69,7 +69,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, logic [$clog2(NUMLINES)-1:0] RAdrD; logic [2**LOGWPL-1:0] MemPAdrDecoded; logic [LINELEN/`XLEN-1:0] SelectedWriteWordEn; - logic [(`XLEN-1)/8:0] FinalByteWEN; + logic [(`XLEN-1)/8:0] FinalByteWe; ///////////////////////////////////////////////////////////////////////////////////////////// // Write Enable demux @@ -78,15 +78,14 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, .bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded)); // If writing the whole line set all write enables to 1, else only set the correct word. assign SelectedWriteWordEn = SetValidWay ? '1 : SetDirtyWay ? MemPAdrDecoded : '0; // OR-AND - assign FinalByteWEN = SetValidWay ? '1 : ByteWEN; // OR - //assign FinalByteWEN = '1;//SetValidWay ? '1 : ByteWEN; // OR + assign FinalByteWe = SetValidWay ? '1 : ByteWe; // OR ///////////////////////////////////////////////////////////////////////////////////////////// // Tag Array ///////////////////////////////////////////////////////////////////////////////////////////// sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, - .Adr(RAdr), .ReadData(ReadTag), .ByteWEN('1), + .Adr(RAdr), .ReadData(ReadTag), .ByteWe('1), .CacheWriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(SetValidWay)); // AND portion of distributed tag multiplexer @@ -105,7 +104,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(`XLEN)) CacheDataMem(.clk, .Adr(RAdr), .ReadData(ReadDataLine[(words+1)*`XLEN-1:words*`XLEN] ), .CacheWriteData(CacheWriteData[(words+1)*`XLEN-1:words*`XLEN]), - .WriteEnable(SelectedWriteWordEn[words]), .ByteWEN(FinalByteWEN)); + .WriteEnable(SelectedWriteWordEn[words]), .ByteWe(FinalByteWe)); end // AND portion of distributed read multiplexers diff --git a/pipelined/src/cache/sram1p1rw.sv b/pipelined/src/cache/sram1p1rw.sv index 06581d0c3..229fb49a2 100644 --- a/pipelined/src/cache/sram1p1rw.sv +++ b/pipelined/src/cache/sram1p1rw.sv @@ -38,7 +38,7 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) ( input logic [$clog2(DEPTH)-1:0] Adr, input logic [WIDTH-1:0] CacheWriteData, input logic WriteEnable, - input logic [(WIDTH-1)/8:0] ByteWEN, + input logic [(WIDTH-1)/8:0] ByteWe, output logic [WIDTH-1:0] ReadData); logic [WIDTH-1:0] StoredData[DEPTH-1:0]; @@ -50,7 +50,7 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) ( genvar index; for(index = 0; index < WIDTH/8; index++) begin always_ff @(posedge clk) begin - if (WriteEnable & ByteWEN[index]) begin + if (WriteEnable & ByteWe[index]) begin StoredData[Adr][8*(index+1)-1:8*index] <= #1 CacheWriteData[8*(index+1)-1:8*index]; end end @@ -58,7 +58,7 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) ( // if not a multiple of 8, MSByte is not 8 bits long. if(WIDTH%8 != 0) begin always_ff @(posedge clk) begin - if (WriteEnable & ByteWEN[WIDTH/8]) begin + if (WriteEnable & ByteWe[WIDTH/8]) begin StoredData[Adr][WIDTH-1:WIDTH-WIDTH%8] <= #1 CacheWriteData[WIDTH-1:WIDTH-WIDTH%8]; end end diff --git a/pipelined/src/generic/flop/simpleram.sv b/pipelined/src/generic/flop/simpleram.sv index 492bb4612..9d17bfe56 100644 --- a/pipelined/src/generic/flop/simpleram.sv +++ b/pipelined/src/generic/flop/simpleram.sv @@ -34,7 +34,7 @@ module simpleram #(parameter BASE=0, RANGE = 65535) ( input logic clk, input logic [31:0] a, input logic we, - input logic [`XLEN/8-1:0] FinalByteWENM, + input logic [`XLEN/8-1:0] ByteWe, input logic [`XLEN-1:0] wd, output logic [`XLEN-1:0] rd ); @@ -52,7 +52,7 @@ module simpleram #(parameter BASE=0, RANGE = 65535) ( genvar index; for(index = 0; index < `XLEN/8; index++) begin always_ff @(posedge clk) begin - if (we & FinalByteWENM[index]) RAM[adrmsbs][8*(index+1)-1:8*index] <= #1 wd[8*(index+1)-1:8*index]; + if (we & ByteWe[index]) RAM[adrmsbs][8*(index+1)-1:8*index] <= #1 wd[8*(index+1)-1:8*index]; end end endmodule diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 2f118b4a3..12b20a322 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -175,7 +175,7 @@ module ifu ( if (`IMEM == `MEM_TIM) begin : irom // *** fix up dtim taking PA_BITS rather than XLEN, *** IEUAdr is a bad name. Probably use a ROM rather than DTIM dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM(PCPF[31:0]), .IEUAdrE(PCNextFSpill), - .TrapM(1'b0), .FinalWriteDataM(), .FinalByteWENM('0), + .TrapM(1'b0), .FinalWriteDataM(), .ByteWeM('0), .ReadDataWordM(AllInstrRawF), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead), .BusCommittedM(), .ReadDataWordMuxM(), .DCacheStallM(ICacheStallF), .DCacheCommittedM(), .DCacheMiss(ICacheMiss), .DCacheAccess(ICacheAccess)); @@ -220,7 +220,7 @@ module ifu ( .CacheWriteLine(), .ReadDataLine(ReadDataLine), .save, .restore, .Cacheable(CacheableF), .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess), - .ByteWEN('0), + .ByteWe('0), .FinalWriteData('0), .RW(2'b10), .Atomic('0), .FlushCache('0), diff --git a/pipelined/src/lsu/dtim.sv b/pipelined/src/lsu/dtim.sv index 70a19367e..dc2e0e126 100644 --- a/pipelined/src/lsu/dtim.sv +++ b/pipelined/src/lsu/dtim.sv @@ -37,7 +37,7 @@ module dtim( input logic [`XLEN-1:0] IEUAdrE, input logic TrapM, input logic [`XLEN-1:0] FinalWriteDataM, - input logic [`XLEN/8-1:0] FinalByteWENM, + input logic [`XLEN/8-1:0] ByteWeM, output logic [`XLEN-1:0] ReadDataWordM, output logic BusStall, output logic LSUBusWrite, @@ -50,7 +50,7 @@ module dtim( output logic DCacheAccess); simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram ( - .clk, .FinalByteWENM, + .clk, .ByteWe(ByteWeM), .a(CPUBusy | LSURWM[0] | reset ? IEUAdrM[31:0] : IEUAdrE[31:0]), // move mux out; this shouldn't be needed when stails are handled differently *** .we(LSURWM[0] & ~TrapM), // have to ignore write if Trap. .wd(FinalWriteDataM), .rd(ReadDataWordM)); diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 8fd94c177..7d543c242 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -105,7 +105,7 @@ module lsu ( logic LSUBusWriteCrit; logic DataDAPageFaultM; logic [`XLEN-1:0] LSUWriteDataM; - logic [(`XLEN-1)/8:0] FinalByteWENM; + logic [(`XLEN-1)/8:0] ByteWeM; // *** TO DO: Burst mode, byte write enables to DTIM, cache, exeternal memory, remove subword write from uncore, @@ -194,7 +194,7 @@ module lsu ( // Merge SimpleRAM and SRAM1p1rw into one that is good for synthesis and RAM libraries and flops dtim dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .FinalWriteDataM, .ReadDataWordM, .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM, - .ReadDataWordMuxM, .DCacheStallM, .DCacheCommittedM, .FinalByteWENM, + .ReadDataWordMuxM, .DCacheStallM, .DCacheCommittedM, .ByteWeM, .DCacheMiss, .DCacheAccess); assign SelUncachedAdr = '0; // value does not matter. end else begin : bus @@ -235,7 +235,7 @@ module lsu ( .NUMWAYS(`DCACHE_NUMWAYS), .DCACHE(1)) dcache( .clk, .reset, .CPUBusy, .save, .restore, .RW(LSURWM), .Atomic(LSUAtomicM), .FlushCache(FlushDCacheM), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM), - .ByteWEN(FinalByteWENM), + .ByteWe(ByteWeM), .FinalWriteData(FinalWriteDataM), .Cacheable(CacheableM), .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), .IgnoreRequestTLB, .IgnoreRequestTrapM, .CacheCommitted(DCacheCommittedM), @@ -255,7 +255,7 @@ module lsu ( subwordwrite subwordwrite(.HADDRD(LSUPAdrM[2:0]), .HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}), - .HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM), .ByteWEN(FinalByteWENM)); + .HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM), .ByteWeM); subwordread subwordread(.ReadDataWordMuxM, .LSUPAdrM(LSUPAdrM[2:0]), .Funct3M(LSUFunct3M), .ReadDataM); diff --git a/pipelined/src/lsu/subwordwrite.sv b/pipelined/src/lsu/subwordwrite.sv index 474035a9b..6756f3128 100644 --- a/pipelined/src/lsu/subwordwrite.sv +++ b/pipelined/src/lsu/subwordwrite.sv @@ -35,14 +35,14 @@ module subwordwrite ( input logic [3:0] HSIZED, input logic [`XLEN-1:0] HWDATAIN, output logic [`XLEN-1:0] HWDATA, - output logic [`XLEN/8-1:0] ByteWEN + output logic [`XLEN/8-1:0] ByteWeM ); logic [`XLEN-1:0] WriteDataSubwordDuplicated; logic [(`XLEN/8)-1:0] ByteMaskM; swbytemask swbytemask(.HSIZED, .HADDRD, .ByteMask(ByteMaskM)); - assign ByteWEN = ByteMaskM; + assign ByteWeM = ByteMaskM; if (`XLEN == 64) begin:sww // Handle subword writes