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Simplified SLT logic
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@ -40,9 +40,9 @@ module alu #(parameter WIDTH=32) (
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logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult;
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logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult;
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logic Carry, Neg;
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logic Carry, Neg;
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logic LT, LTU;
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logic LT, LTU;
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logic Overflow;
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logic W64, SubArith, ALUOp;
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logic W64, SubArith, ALUOp;
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logic [2:0] ALUFunct;
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logic [2:0] ALUFunct;
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logic Asign, Bsign;
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// Extract control signals
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// Extract control signals
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// W64 indicates RV64 W-suffix instructions acting on lower 32-bit word
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// W64 indicates RV64 W-suffix instructions acting on lower 32-bit word
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@ -57,12 +57,13 @@ module alu #(parameter WIDTH=32) (
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// Shifts
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// Shifts
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shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift));
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shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift));
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// condition code flags based on subtract output
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// condition code flags based on subtract output Sum = A-B
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// Overflow occurs when the numbers being subtracted have the opposite sign
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// Overflow occurs when the numbers being subtracted have the opposite sign
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// and the result has the opposite sign of A
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// and the result has the opposite sign of A
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assign Overflow = (A[WIDTH-1] ^ B[WIDTH-1]) & (A[WIDTH-1] ^ Sum[WIDTH-1]);
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assign Neg = Sum[WIDTH-1];
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assign Neg = Sum[WIDTH-1];
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assign LT = Neg ^ Overflow;
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assign Asign = A[WIDTH-1];
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assign Bsign = B[WIDTH-1];
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assign LT = Asign & ~Bsign | Asign & Neg | ~Bsign & Neg; // simplified from Overflow = Asign & Bsign & Asign & Neg; LT = Neg ^ Overflow
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assign LTU = ~Carry;
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assign LTU = ~Carry;
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// SLT
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// SLT
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