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Simplified SLT logic

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David Harris 2022-04-17 16:49:51 +00:00
parent 55c667b60d
commit d71940d96d
1 changed files with 5 additions and 4 deletions
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9
pipelined/src/ieu/alu.sv
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@ -40,9 +40,9 @@ module alu #(parameter WIDTH=32) (
logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult; logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult;
logic Carry, Neg; logic Carry, Neg;
logic LT, LTU; logic LT, LTU;
logic Overflow;
logic W64, SubArith, ALUOp; logic W64, SubArith, ALUOp;
logic [2:0] ALUFunct; logic [2:0] ALUFunct;
logic Asign, Bsign;
// Extract control signals // Extract control signals
// W64 indicates RV64 W-suffix instructions acting on lower 32-bit word // W64 indicates RV64 W-suffix instructions acting on lower 32-bit word
@ -57,12 +57,13 @@ module alu #(parameter WIDTH=32) (
// Shifts // Shifts
shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift)); shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift));
// condition code flags based on subtract output // condition code flags based on subtract output Sum = A-B
// Overflow occurs when the numbers being subtracted have the opposite sign // Overflow occurs when the numbers being subtracted have the opposite sign
// and the result has the opposite sign of A // and the result has the opposite sign of A
assign Overflow = (A[WIDTH-1] ^ B[WIDTH-1]) & (A[WIDTH-1] ^ Sum[WIDTH-1]);
assign Neg = Sum[WIDTH-1]; assign Neg = Sum[WIDTH-1];
assign LT = Neg ^ Overflow; assign Asign = A[WIDTH-1];
assign Bsign = B[WIDTH-1];
assign LT = Asign & ~Bsign | Asign & Neg | ~Bsign & Neg; // simplified from Overflow = Asign & Bsign & Asign & Neg; LT = Neg ^ Overflow
assign LTU = ~Carry; assign LTU = ~Carry;
// SLT // SLT