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Fixed bus width error. Have to check this FPGA to make sure this didn't break anything.

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This commit is contained in:
Rose Thompson 2024-07-23 12:26:03 -05:00
parent b30656447f
commit d706b5b898
1 changed files with 2 additions and 2 deletions
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4
src/rvvi/packetizer.sv
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@ -42,7 +42,7 @@ module packetizer import cvw::*; #(parameter cvw_t P,
input logic RvviAxiWready
);
localparam TotalFrameLengthBits = 2*48+32+16+187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12);
localparam TotalFrameLengthBits = 2*48+17+16+187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12);
localparam TotalFrameLengthBytes = TotalFrameLengthBits / 8;
logic [9:0] WordCount;
@ -121,7 +121,7 @@ module packetizer import cvw::*; #(parameter cvw_t P,
end
assign Length = {4'b0, BytesInFrame};
assign TotalFrame = {16'b0, rvviDelay, EthType, DstMac, SrcMac};
assign TotalFrame = {17'b0, rvviDelay, EthType, DstMac, SrcMac};
// *** fix me later
assign DstMac = 48'h8F54_0000_1654; // made something up