diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py
index a997c2a7b..bd703a017 100755
--- a/wally-pipelined/regression/regression-wally.py
+++ b/wally-pipelined/regression/regression-wally.py
@@ -10,6 +10,7 @@
 # output.
 #
 ##################################
+import sys
 
 from collections import namedtuple
 TestCase = namedtuple("TestCase", ['name', 'cmd', 'grepstr'])
@@ -23,22 +24,22 @@ TestCase = namedtuple("TestCase", ['name', 'cmd', 'grepstr'])
 
 # edit this list to add more test cases
 configs = [
-    #TestCase(
-    #    name="busybear",
-    #    cmd="vsim -do wally-busybear-batch.do -c > {}",
-    #    grepstr="loaded 100000 instructions"
-    #),
-    TestCase(
-        name="buildroot",
-        cmd="vsim -do wally-buildroot-batch.do -c > {}",
-        grepstr="6300000 instructions"
-    ),
     TestCase(
         name="lints",
         cmd="./lint-wally &> {}",
         grepstr="All lints run with no errors or warnings"
-    ),
+    )
 ]
+def getBuildrootTC(short):
+    INSTR_LIMIT = 100000 # multiple of 100000
+    MAX_EXPECTED = 6.3e6
+    if short:
+        BRcmd="vsim > {} -c <<!\ndo wally-buildroot-batch.do "+str(INSTR_LIMIT)+"\n!"
+        BRgrepstr=str(INSTR_LIMIT)+" instructions"
+    else:
+        BRcmd="vsim > {} -c <<!\ndo wally-buildroot-batch.do 0\n!"
+        BRgrepstr=str(MAX_EXPECTED)+" instructions"
+    return  TestCase(name="buildroot",cmd=BRcmd,grepstr=BRgrepstr)
 
 tests64 = ["arch64i", "arch64priv", "arch64c",  "arch64m", "imperas64i", "imperas64p", "imperas64mmu", "imperas64f", "imperas64d", "imperas64m", "imperas64a",  "imperas64c"] #,  "testsBP64"]
 for test in tests64:
@@ -83,7 +84,15 @@ def main():
     """Run the tests and count the failures"""
     # Scale the number of concurrent processes to the number of test cases, but
     # max out at a limited number of concurrent processes to not overwhelm the system
-    TIMEOUT_DUR = 1800 # seconds
+
+    if '-all' in sys.argv:
+        TIMEOUT_DUR = 3600 
+        configs.append(getBuildrootTC(short=False))
+    else:
+        TIMEOUT_DUR = 300
+        configs.append(getBuildrootTC(short=True))
+    print(configs)
+
     try:
         os.mkdir("logs")
     except:
diff --git a/wally-pipelined/regression/sim-buildroot-batch b/wally-pipelined/regression/sim-buildroot-batch
index efb09c9a0..e135b832a 100755
--- a/wally-pipelined/regression/sim-buildroot-batch
+++ b/wally-pipelined/regression/sim-buildroot-batch
@@ -1,3 +1,4 @@
+INSTR_LIMIT=${1:-0}
 vsim -c <<!
-do wally-buildroot-batch.do 
+do wally-buildroot-batch.do $INSTR_LIMIT
 !
diff --git a/wally-pipelined/regression/wally-buildroot-batch.do b/wally-pipelined/regression/wally-buildroot-batch.do
index bca3ca35e..2fedcfa99 100644
--- a/wally-pipelined/regression/wally-buildroot-batch.do
+++ b/wally-pipelined/regression/wally-buildroot-batch.do
@@ -30,7 +30,7 @@ vlog +incdir+../config/buildroot +incdir+../config/shared ../testbench/testbench
 
 # start and run simulation
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals
-vopt work.testbench -o workopt 
+vopt work.testbench -G INSTR_LIMIT=$1 -o workopt 
 
 vsim workopt -suppress 8852,12070
 
diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv
index 6731aabcd..4a35c757b 100644
--- a/wally-pipelined/testbench/testbench-linux.sv
+++ b/wally-pipelined/testbench/testbench-linux.sv
@@ -38,7 +38,9 @@
 
 module testbench();
   
-  parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*6300000; // # of instructions at which to turn on waves in graphical sim
+  parameter INSTR_LIMIT = 0; // # of instructions at which to stop
+  parameter INSTR_WAVEON = (INSTR_LIMIT > 10000) ? INSTR_LIMIT-10000 : 1; // # of instructions at which to turn on waves in graphical sim
+
   string ProgramAddrMapFile, ProgramLabelMapFile;
 
   ///////////////////////////////////////////////////////////////////////////////
@@ -343,10 +345,12 @@ module testbench();
     // always check PC, instruction bits
     if (checkInstrW) begin
       InstrCountW += 1;
-      // turn on waves at certain point
-      if (InstrCountW == waveOnICount) $stop;
       // print progress message
       if (InstrCountW % 'd100000 == 0) $display("Reached %d instructions", InstrCountW);
+      // turn on waves
+      if (InstrCountW == INSTR_WAVEON) $stop;
+      // end sim
+      if ((InstrCountW == INSTR_LIMIT) && (INSTR_LIMIT!=0)) $stop;
       fault = 0;
       if (`DEBUG_TRACE >= 1) begin
         `checkEQ("PCW",PCW,ExpectedPCW)
@@ -423,8 +427,8 @@ module testbench();
   initial begin
     $readmemh({`LINUX_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootdtim.bootdtim.RAM, 'h1000 >> 3);
     $readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM);
-    $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
-    $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory);
+    $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
+    $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.mem);
     ProgramAddrMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.addr"};
     ProgramLabelMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.lab"};
   end