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https://github.com/openhwgroup/cvw
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Modified sram1p1rw to support 3 different implementation styles.
SRAM, Read first, and Write first.
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pipelined/src/cache/sram1p1rw.sv
vendored
83
pipelined/src/cache/sram1p1rw.sv
vendored
@ -35,7 +35,16 @@
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`include "wally-config.vh"
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`include "wally-config.vh"
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module sram1p1rw #(parameter DEPTH=128, WIDTH=256) (
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// SRAM is hard sram macro
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// read first is a verilog model of SRAM with extra hardware to make it appear as write first.
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// write first is a verilog model of flops which implements write first behavior.
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// If the goal is to use flops use write first. This implements the least amount of hardware for
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// the ram. If the goal is to use SRAM use SRAM This currently only supports 64x128 SRAMs.
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// If the goal is model SRAM behavior then use READ_FIRST. sram1p1rw adds extra hardware to
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// ensure write first behavior is observered.
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module sram1p1rw #(parameter DEPTH=128, WIDTH=256, RAM_TYPE = "READ_FIRST") (
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input logic clk,
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input logic clk,
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input logic ce,
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input logic ce,
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input logic [$clog2(DEPTH)-1:0] Adr,
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input logic [$clog2(DEPTH)-1:0] Adr,
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@ -45,39 +54,75 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) (
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output logic [WIDTH-1:0] ReadData);
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output logic [WIDTH-1:0] ReadData);
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logic [WIDTH-1:0] StoredData[DEPTH-1:0];
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logic [WIDTH-1:0] StoredData[DEPTH-1:0];
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logic [$clog2(DEPTH)-1:0] AdrD;
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logic [WIDTH-1:0] ReadDataInternal, WriteDataD;
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logic WriteEnableD;
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always_ff @(posedge clk) if(ce) AdrD <= Adr;
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genvar index;
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if (`USE_SRAM == 1) begin
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// ***************************************************************************
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// TRUE SRAM macro
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// ***************************************************************************
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if (RAM_TYPE == "SRAM") begin
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genvar index;
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// 64 x 128-bit SRAM
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// 64 x 128-bit SRAM
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// check if the size is ok, complain if not***
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// check if the size is ok, complain if not***
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logic [WIDTH-1:0] BitWriteMask;
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logic [WIDTH-1:0] BitWriteMask;
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for (index=0; index < WIDTH; index++)
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for (index=0; index < WIDTH; index++)
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assign BitWriteMask[index] = ByteMask[index/8];
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assign BitWriteMask[index] = ByteMask[index/8];
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TS1N28HPCPSVTB64X128M4SWBASO sram(
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TS1N28HPCPSVTB64X128M4SW sram(
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.CLK(clk), .CEB(1'b0), .WEB(~WriteEnable),
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.CLK(clk), .CEB(~ce), .WEB(~WriteEnable),
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.A(Adr), .D(CacheWriteData),
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.A(Adr), .D(CacheWriteData),
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.BWEB(~BitWriteMask), .Q(ReadData)
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.BWEB(~BitWriteMask), .Q(ReadDataInternal));
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);
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end else begin
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// ***************************************************************************
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// Correctly modeled SRAM as read first
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// ***************************************************************************
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end else if (RAM_TYPE == "READ_FIRST") begin
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integer index2;
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if (WIDTH%8 != 0) // handle msbs if not a multiple of 8
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if (WIDTH%8 != 0) // handle msbs if not a multiple of 8
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always_ff @(posedge clk)
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always_ff @(posedge clk)
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if (ce & WriteEnable & ByteMask[WIDTH/8])
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if (ce & WriteEnable & ByteMask[WIDTH/8])
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StoredData[Adr][WIDTH-1:WIDTH-WIDTH%8] <= #1
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StoredData[Adr][WIDTH-1:WIDTH-WIDTH%8] <= #1 CacheWriteData[WIDTH-1:WIDTH-WIDTH%8];
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CacheWriteData[WIDTH-1:WIDTH-WIDTH%8];
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for(index = 0; index < WIDTH/8; index++)
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always_ff @(posedge clk) begin
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if(ce) begin
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if(WriteEnable) begin
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for(index2 = 0; index2 < WIDTH/8; index2++)
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if(ce & WriteEnable & ByteMask[index2])
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StoredData[Adr][index2*8 +: 8] <= #1 CacheWriteData[index2*8 +: 8];
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end
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ReadDataInternal <= #1 StoredData[Adr];
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end
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end
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always_ff @(posedge clk) begin
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if(ce) begin
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WriteEnableD <= WriteEnable;
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if(WriteEnable) WriteDataD <= #1 CacheWriteData;
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end
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end
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assign ReadData = WriteEnableD ? WriteDataD : ReadDataInternal; // convert to Write First SRAM by forwarding the write data on write
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// ***************************************************************************
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// Memory modeled as wrire first. best as flip flop implementation.
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// ***************************************************************************
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end else if (RAM_TYPE == "WRITE_FIRST") begin
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logic [$clog2(DEPTH)-1:0] AdrD;
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flopen #($clog2(DEPTH)) RAdrDelayReg(clk, ce, Adr, AdrD);
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integer index2;
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if (WIDTH%8 != 0) // handle msbs if not a multiple of 8
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always_ff @(posedge clk)
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always_ff @(posedge clk)
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if(ce & WriteEnable & ByteMask[index])
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if (ce & WriteEnable & ByteMask[WIDTH/8])
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StoredData[Adr][index*8 +: 8] <= #1 CacheWriteData[index*8 +: 8];
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StoredData[Adr][WIDTH-1:WIDTH-WIDTH%8] <= #1 CacheWriteData[WIDTH-1:WIDTH-WIDTH%8];
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always_ff @(posedge clk) begin
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if(ce) begin
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if(WriteEnable) begin
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for(index2 = 0; index2 < WIDTH/8; index2++)
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if(ce & WriteEnable & ByteMask[index2])
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StoredData[Adr][index2*8 +: 8] <= #1 CacheWriteData[index2*8 +: 8];
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end
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end
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end
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assign ReadData = StoredData[AdrD];
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assign ReadData = StoredData[AdrD];
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end
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end
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endmodule
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endmodule
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