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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally

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This commit is contained in:
Katherine Parry 2022-07-18 17:31:29 +00:00
commit d6f1fc12db
4 changed files with 17 additions and 6 deletions
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4
pipelined/src/uncore/plic_apb.sv
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@ -172,8 +172,8 @@ module plic_apb (
end end
// pending interrupt requests // pending interrupt requests
//assign nextIntPending = (intPending | requests) & ~intInProgress; // assign nextIntPending = (intPending | requests) & ~intInProgress; // dh changed back 7/9/22 see if Buildroot still boots. Confirmed to boot successfully.
assign nextIntPending = requests; // DH: RT made this change May 2022, but it seems to be a bug to not consider intInProgress; see May 23, 2022 slack discussion //assign nextIntPending = requests; // DH: RT made this change May 2022, but it seems to be a bug to not consider intInProgress; see May 23, 2022 slack discussion
flopr #(`N) intPendingFlop(PCLK,~PRESETn,nextIntPending,intPending); flopr #(`N) intPendingFlop(PCLK,~PRESETn,nextIntPending,intPending);
// context-dependent signals // context-dependent signals

2
synthDC/Makefile
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@ -107,7 +107,7 @@ ifeq ($(SAIFPOWER), 1)
cp -f ../pipelined/regression/power.saif . cp -f ../pipelined/regression/power.saif .
endif endif
dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out
rm -rf $(OUTPUTDIR)/hdl # rm -rf $(OUTPUTDIR)/hdl
rm -rf $(OUTPUTDIR)/WORK rm -rf $(OUTPUTDIR)/WORK
rm -rf $(OUTPUTDIR)/alib-52 rm -rf $(OUTPUTDIR)/alib-52

11
synthDC/extractSummary.py
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@ -11,6 +11,7 @@ import numpy as np
from ppa.ppaAnalyze import noOutliers from ppa.ppaAnalyze import noOutliers
from matplotlib import ticker from matplotlib import ticker
import argparse import argparse
import os
def synthsintocsv(): def synthsintocsv():
@ -59,6 +60,7 @@ def synthsintocsv():
writer.writerow([width, config, special, tech, freq, delay, area]) writer.writerow([width, config, special, tech, freq, delay, area])
file.close() file.close()
def synthsfromcsv(filename): def synthsfromcsv(filename):
Synth = namedtuple("Synth", "width config special tech freq delay area") Synth = namedtuple("Synth", "width config special tech freq delay area")
with open(filename, newline='') as csvfile: with open(filename, newline='') as csvfile:
@ -74,10 +76,16 @@ def synthsfromcsv(filename):
allSynths[i] = Synth(*allSynths[i]) allSynths[i] = Synth(*allSynths[i])
return allSynths return allSynths
def freqPlot(tech, width, config): def freqPlot(tech, width, config):
''' plots delay, area for syntheses with specified tech, module, width ''' plots delay, area for syntheses with specified tech, module, width
''' '''
current_directory = os.getcwd()
final_directory = os.path.join(current_directory, 'plots/wally')
if not os.path.exists(final_directory):
os.makedirs(final_directory)
freqsL, delaysL, areasL = ([[], []] for i in range(3)) freqsL, delaysL, areasL = ([[], []] for i in range(3))
for oneSynth in allSynths: for oneSynth in allSynths:
if (width == oneSynth.width) & (config == oneSynth.config) & (tech == oneSynth.tech) & ('' == oneSynth.special): if (width == oneSynth.width) & (config == oneSynth.config) & (tech == oneSynth.tech) & ('' == oneSynth.special):
@ -151,6 +159,7 @@ def areaDelay(tech, delays, areas, labels, fig, ax, norm=False):
return fig return fig
def plotFeatures(tech, width, config): def plotFeatures(tech, width, config):
delays, areas, labels = ([] for i in range(3)) delays, areas, labels = ([] for i in range(3))
freq = techdict[tech].targfreq freq = techdict[tech].targfreq
@ -169,6 +178,7 @@ def plotFeatures(tech, width, config):
plt.title(titlestr) plt.title(titlestr)
plt.savefig('./plots/wally/features_'+titlestr+'.png') plt.savefig('./plots/wally/features_'+titlestr+'.png')
def plotConfigs(tech, special=''): def plotConfigs(tech, special=''):
delays, areas, labels = ([] for i in range(3)) delays, areas, labels = ([] for i in range(3))
freq = techdict[tech].targfreq freq = techdict[tech].targfreq
@ -208,6 +218,7 @@ def normAreaDelay(special=''):
ax.legend(handles = fullLeg, loc='upper left') ax.legend(handles = fullLeg, loc='upper left')
plt.savefig('./plots/wally/normAreaDelay.png') plt.savefig('./plots/wally/normAreaDelay.png')
def addFO4axis(fig, ax, tech): def addFO4axis(fig, ax, tech):
fo4 = techdict[tech].fo4 fo4 = techdict[tech].fo4

2
synthDC/scripts/synth.tcl
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@ -56,7 +56,7 @@ set vhdlout_show_unconnected_pins "true"
# Due to parameterized Verilog must use analyze/elaborate and not # Due to parameterized Verilog must use analyze/elaborate and not
# read_verilog/vhdl (change to pull in Verilog and/or VHDL) # read_verilog/vhdl (change to pull in Verilog and/or VHDL)
# #
set alib_library_analysis_path ./$outputDir #set alib_library_analysis_path ./$outputDir
define_design_lib WORK -path ./$outputDir/WORK define_design_lib WORK -path ./$outputDir/WORK
analyze -f sverilog -lib WORK $my_verilog_files analyze -f sverilog -lib WORK $my_verilog_files
elaborate $my_toplevel -lib WORK elaborate $my_toplevel -lib WORK