diff --git a/pipelined/src/cache/AHBBuscachefsm.sv b/pipelined/src/cache/AHBBuscachefsm.sv
deleted file mode 100644
index d8f786535..000000000
--- a/pipelined/src/cache/AHBBuscachefsm.sv
+++ /dev/null
@@ -1,163 +0,0 @@
-///////////////////////////////////////////
-// busfsm.sv
-//
-// Written: Ross Thompson ross1728@gmail.com December 29, 2021
-// Modified:
-//
-// Purpose: Load/Store Unit's interface to BUS for cacheless system
-//
-// A component of the Wally configurable RISC-V project.
-//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// MIT LICENSE
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this
-// software and associated documentation files (the "Software"), to deal in the Software
-// without restriction, including without limitation the rights to use, copy, modify, merge,
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
-// to whom the Software is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or
-// substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
-// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
-// OR OTHER DEALINGS IN THE SOFTWARE.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`include "wally-config.vh"
-
-// HCLK and clk must be the same clock!
-module AHBBuscachefsm #(parameter integer WordCountThreshold,
- parameter integer LOGWPL, parameter logic CACHE_ENABLED )
- (input logic HCLK,
- input logic HRESETn,
-
- // IEU interface
- input logic [1:0] RW,
- input logic CPUBusy,
- output logic BusCommitted,
- output logic BusStall,
- output logic CaptureEn,
-
- // cache interface
- input logic [1:0] CacheRW,
- output logic CacheBusAck,
-
- // lsu interface
- output logic SelUncachedAdr,
- output logic [LOGWPL-1:0] WordCount, WordCountDelayed,
- output logic SelBusWord,
-
- // BUS interface
- input logic HREADY,
- output logic [1:0] HTRANS,
- output logic HWRITE,
- output logic [2:0] HBURST
-);
-
- typedef enum logic [2:0] {STATE_READY,
- STATE_CAPTURE,
- STATE_DELAY,
- STATE_CPU_BUSY,
- STATE_CACHE_FETCH,
- STATE_CACHE_EVICT} busstatetype;
-
- typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype;
-
- (* mark_debug = "true" *) busstatetype BusCurrState, BusNextState;
-
- logic [LOGWPL-1:0] NextWordCount;
- logic FinalWordCount;
- logic [2:0] LocalBurstType;
- logic WordCntEn;
- logic WordCntReset;
- logic CacheAccess;
-
- always_ff @(posedge HCLK)
- if (~HRESETn) BusCurrState <= #1 STATE_READY;
- else BusCurrState <= #1 BusNextState;
-
- always_comb begin
- case(BusCurrState)
- STATE_READY: if(HREADY & |RW) BusNextState = STATE_CAPTURE;
- else if (HREADY & CacheRW[0]) BusNextState = STATE_CACHE_EVICT;
- else if (HREADY & CacheRW[1]) BusNextState = STATE_CACHE_FETCH;
- else BusNextState = STATE_READY;
- STATE_CAPTURE: if(HREADY) BusNextState = STATE_DELAY;
- else BusNextState = STATE_CAPTURE;
- STATE_DELAY: if(CPUBusy) BusNextState = STATE_CPU_BUSY;
- else BusNextState = STATE_READY;
- STATE_CPU_BUSY: if(CPUBusy) BusNextState = STATE_CPU_BUSY;
- else BusNextState = STATE_READY;
- STATE_CACHE_FETCH: if(HREADY & FinalWordCount) BusNextState = STATE_READY;
- else BusNextState = STATE_CACHE_FETCH;
- STATE_CACHE_EVICT: if(HREADY & FinalWordCount) BusNextState = STATE_READY;
- else BusNextState = STATE_CACHE_EVICT;
- default: BusNextState = STATE_READY;
- endcase
- end
-
- // IEU, LSU, and IFU controls
- flopenr #(LOGWPL)
- WordCountReg(.clk(HCLK),
- .reset(~HRESETn | WordCntReset),
- .en(WordCntEn),
- .d(NextWordCount),
- .q(WordCount));
-
- // Used to store data from data phase of AHB.
- flopenr #(LOGWPL)
- WordCountDelayedReg(.clk(HCLK),
- .reset(~HRESETn | WordCntReset),
- .en(WordCntEn),
- .d(WordCount),
- .q(WordCountDelayed));
- assign NextWordCount = WordCount + 1'b1;
-
- assign FinalWordCount = WordCountDelayed == WordCountThreshold[LOGWPL-1:0];
- assign WordCntEn = ((BusNextState == STATE_CACHE_EVICT | BusNextState == STATE_CACHE_FETCH) & HREADY) |
- (BusNextState == STATE_READY & |CacheRW & HREADY);
- assign WordCntReset = BusNextState == STATE_READY;
-
- assign CaptureEn = (BusCurrState == STATE_CAPTURE & RW[1]) | (BusCurrState == STATE_CACHE_FETCH & HREADY);
- assign CacheAccess = BusCurrState == STATE_CACHE_FETCH | BusCurrState == STATE_CACHE_EVICT;
-
- assign BusStall = (BusCurrState == STATE_READY & (|RW | |CacheRW)) |
- (BusCurrState == STATE_CAPTURE) |
- (BusCurrState == STATE_CACHE_FETCH) |
- (BusCurrState == STATE_CACHE_EVICT);
- assign BusCommitted = BusCurrState != STATE_READY;
- assign SelUncachedAdr = (BusCurrState == STATE_READY & |RW) |
- (BusCurrState == STATE_CAPTURE) |
- (BusCurrState == STATE_DELAY);
-
- // AHB bus interface
- assign HTRANS = (BusCurrState == STATE_READY & HREADY & (|RW | |CacheRW)) |
- (BusCurrState == STATE_CAPTURE & ~HREADY) |
- (CacheAccess & ~HREADY & ~|WordCount) ? AHB_NONSEQ :
- (CacheAccess & |WordCount) ? AHB_SEQ : AHB_IDLE;
-
- assign HWRITE = RW[0] | CacheRW[0];
- assign HBURST = (|CacheRW) ? LocalBurstType : 3'b0;
-
- always_comb begin
- case(WordCountThreshold)
- 0: LocalBurstType = 3'b000;
- 3: LocalBurstType = 3'b011; // INCR4
- 7: LocalBurstType = 3'b101; // INCR8
- 15: LocalBurstType = 3'b111; // INCR16
- default: LocalBurstType = 3'b001; // INCR without end.
- endcase
- end
-
- // communication to cache
- assign CacheBusAck = (CacheAccess & HREADY & FinalWordCount);
- assign SelBusWord = (BusCurrState == STATE_READY & (RW[0] | CacheRW[0])) |
- (BusCurrState == STATE_CAPTURE & RW[0]) |
- (BusCurrState == STATE_CACHE_EVICT);
-
-endmodule
diff --git a/pipelined/src/cache/AHBCachedp.sv b/pipelined/src/cache/AHBCachedp.sv
deleted file mode 100644
index de43c2d98..000000000
--- a/pipelined/src/cache/AHBCachedp.sv
+++ /dev/null
@@ -1,89 +0,0 @@
-///////////////////////////////////////////
-// AHBCachedp.sv
-//
-// Written: Ross Thompson ross1728@gmail.com August 29, 2022
-// Modified:
-//
-// Purpose: Cache/Bus data path.
-// Bus Side logic
-// register the fetch data from the next level of memory.
-// This register should be necessary for timing. There is no register in the uncore or
-// ahblite controller between the memories and this cache.
-//
-// A component of the Wally configurable RISC-V project.
-//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// MIT LICENSE
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this
-// software and associated documentation files (the "Software"), to deal in the Software
-// without restriction, including without limitation the rights to use, copy, modify, merge,
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
-// to whom the Software is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or
-// substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
-// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
-// OR OTHER DEALINGS IN THE SOFTWARE.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`include "wally-config.vh"
-
-module AHBCachedp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
- (
- input logic HCLK, HRESETn,
-
- // bus interface
- input logic HREADY,
- input logic [`XLEN-1:0] HRDATA,
- output logic [2:0] HSIZE,
- output logic [2:0] HBURST,
- output logic [1:0] HTRANS,
- output logic HWRITE,
- output logic [`PA_BITS-1:0] HADDR,
- output logic [LOGWPL-1:0] WordCount,
-
- // cache interface
- input logic [`PA_BITS-1:0] CacheBusAdr,
- input logic [1:0] CacheRW,
- output logic CacheBusAck,
- output logic [LINELEN-1:0] FetchBuffer,
- output logic SelUncachedAdr,
-
- // lsu/ifu interface
- input logic [`PA_BITS-1:0] PAdr,
- input logic [1:0] RW,
- input logic CPUBusy,
- input logic [2:0] Funct3,
- output logic SelBusWord,
- output logic BusStall,
- output logic BusCommitted);
-
- localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0;
- logic [`PA_BITS-1:0] LocalHADDR;
- logic [LOGWPL-1:0] WordCountDelayed;
- logic CaptureEn;
-
- genvar index;
- for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
- logic [WORDSPERLINE-1:0] CaptureWord;
- assign CaptureWord[index] = CaptureEn & (index == WordCountDelayed);
- flopen #(`XLEN) fb(.clk(HCLK), .en(CaptureWord[index]), .d(HRDATA),
- .q(FetchBuffer[(index+1)*`XLEN-1:index*`XLEN]));
- end
-
- mux2 #(`PA_BITS) localadrmux(CacheBusAdr, PAdr, SelUncachedAdr, LocalHADDR);
- assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalHADDR;
-
- mux2 #(3) sizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(Funct3), .s(SelUncachedAdr), .y(HSIZE));
-
- AHBBuscachefsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm(
- .HCLK, .HRESETn, .RW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusWord,
- .CacheRW, .CacheBusAck, .SelUncachedAdr, .WordCount, .WordCountDelayed,
- .HREADY, .HTRANS, .HWRITE, .HBURST);
-endmodule
diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv
deleted file mode 100644
index c27c03069..000000000
--- a/pipelined/src/ebu/ahblite.sv
+++ /dev/null
@@ -1,141 +0,0 @@
-///////////////////////////////////////////
-// ahblite.sv
-//
-// Written: David_Harris@hmc.edu 9 January 2021
-// Modified:
-//
-// Purpose: AHB Lite External Bus Unit
-// See ARM_HIH0033A_AMBA_AHB-Lite_SPEC 1.0
-// Arbitrates requests from instruction and data streams
-// Connects core to peripherals and I/O pins on SOC
-// Bus width presently matches XLEN
-// Anticipate replacing this with an AXI bus interface to communicate with FPGA DRAM/Flash controllers
-//
-// A component of the Wally configurable RISC-V project.
-//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// MIT LICENSE
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this
-// software and associated documentation files (the "Software"), to deal in the Software
-// without restriction, including without limitation the rights to use, copy, modify, merge,
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
-// to whom the Software is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or
-// substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
-// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
-// OR OTHER DEALINGS IN THE SOFTWARE.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`include "wally-config.vh"
-
-module ahblite (
- input logic clk, reset,
- // Load control
- input logic UnsignedLoadM,
- input logic [1:0] AtomicMaskedM,
- // Signals from Instruction Cache
- input logic [`PA_BITS-1:0] IFUHADDR,
- input logic [2:0] IFUHBURST,
- input logic [1:0] IFUHTRANS,
- input logic IFUBusRead,
- input logic IFUTransComplete,
- logic IFUHWRITE,
- logic IFUHREADY,
- output logic IFUBusInit,
- output logic IFUBusAck,
-
- // Signals from Data Cache
- input logic [`PA_BITS-1:0] LSUHADDR,
- input logic [`XLEN-1:0] LSUHWDATA, // initially support AHBW = XLEN
- input logic [2:0] LSUHSIZE,
- input logic [2:0] LSUHBURST,
- input logic [1:0] LSUHTRANS,
- input logic LSUBusRead,
- input logic LSUBusWrite,
- input logic LSUTransComplete,
- logic LSUHWRITE,
- logic LSUHREADY,
- output logic LSUBusInit,
- output logic LSUBusAck,
-
- // AHB-Lite external signals
- (* mark_debug = "true" *) input logic HREADY, HRESP,
- (* mark_debug = "true" *) output logic HCLK, HRESETn,
- (* mark_debug = "true" *) output logic [`PA_BITS-1:0] HADDR, // *** one day switch to a different bus that supports the full physical address
- (* mark_debug = "true" *) output logic [`AHBW-1:0] HWDATA,
- output logic [`XLEN/8-1:0] HWSTRB,
- (* mark_debug = "true" *) output logic HWRITE,
- (* mark_debug = "true" *) output logic [2:0] HSIZE,
- (* mark_debug = "true" *) output logic [2:0] HBURST,
- (* mark_debug = "true" *) output logic [3:0] HPROT,
- (* mark_debug = "true" *) output logic [1:0] HTRANS,
- (* mark_debug = "true" *) output logic HMASTLOCK
-);
-
- localparam ADRBITS = $clog2(`XLEN/8); // address bits for Byte Mask generator
-
- typedef enum logic [1:0] {IDLE, MEMREAD, MEMWRITE, INSTRREAD} statetype;
- statetype BusState, NextBusState;
- logic LSUGrant;
- logic [ADRBITS-1:0] HADDRD;
- logic [1:0] HSIZED;
-
- assign HCLK = clk;
- assign HRESETn = ~reset;
-
- // Bus State FSM
- // Data accesses have priority over instructions. However, if a data access comes
- // while an cache line read is occuring, the line read finishes before
- // the data access can take place.
-
- flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextBusState, IDLE, BusState);
- always_comb
- case (BusState)
- IDLE: if (LSUBusRead) NextBusState = MEMREAD; // Memory has priority over instructions
- else if (LSUBusWrite) NextBusState = MEMWRITE;
- else if (IFUBusRead) NextBusState = INSTRREAD;
- else NextBusState = IDLE;
- MEMREAD: if (LSUTransComplete & IFUBusRead) NextBusState = INSTRREAD;
- else if (LSUTransComplete) NextBusState = IDLE;
- else NextBusState = MEMREAD;
- MEMWRITE: if (LSUTransComplete & IFUBusRead) NextBusState = INSTRREAD;
- else if (LSUTransComplete) NextBusState = IDLE;
- else NextBusState = MEMWRITE;
- INSTRREAD: if (IFUTransComplete & LSUBusRead) NextBusState = MEMREAD;
- else if (IFUTransComplete & LSUBusWrite) NextBusState = MEMWRITE;
- else if (IFUTransComplete) NextBusState = IDLE;
- else NextBusState = INSTRREAD;
- default: NextBusState = IDLE;
- endcase
-
- // LSU/IFU mux: choose source of access
- assign #1 LSUGrant = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE);
- assign HADDR = LSUGrant ? LSUHADDR : IFUHADDR;
- assign HSIZE = LSUGrant ? {1'b0, LSUHSIZE[1:0]} : 3'b010; // Instruction reads are always 32 bits
- assign HBURST = LSUGrant ? LSUHBURST : IFUHBURST; // If doing memory accesses, use LSUburst, else use Instruction burst.
- assign HTRANS = LSUGrant ? LSUHTRANS : IFUHTRANS; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise
- assign HPROT = 4'b0011; // not used; see Section 3.7
- assign HMASTLOCK = 0; // no locking supported
- assign HWRITE = (NextBusState == MEMWRITE);
-
- // delay write data by one cycle for
- flopen #(`XLEN) wdreg(HCLK, (LSUBusAck | LSUBusInit), LSUHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
-
- // Byte mask for HWSTRB based on delayed signals
- flop #(ADRBITS) adrreg(HCLK, HADDR[ADRBITS-1:0], HADDRD);
- flop #(2) sizereg(HCLK, HSIZE[1:0], HSIZED);
- swbytemask swbytemask(.Size({1'b0, HSIZED}), .Adr(HADDRD), .ByteMask(HWSTRB));
-
- // Send control back to IFU and LSU
- assign IFUBusInit = (BusState != INSTRREAD) & (NextBusState == INSTRREAD);
- assign LSUBusInit = (((BusState != MEMREAD) & (NextBusState == MEMREAD)) | (BusState != MEMWRITE) & (NextBusState == MEMWRITE));
- assign IFUBusAck = HREADY & (BusState == INSTRREAD);
- assign LSUBusAck = HREADY & ((BusState == MEMREAD) | (BusState == MEMWRITE));
-endmodule
diff --git a/pipelined/src/lsu/AHBBusfsm.sv b/pipelined/src/lsu/AHBBusfsm.sv
deleted file mode 100644
index b88d5ed47..000000000
--- a/pipelined/src/lsu/AHBBusfsm.sv
+++ /dev/null
@@ -1,86 +0,0 @@
-///////////////////////////////////////////
-// busfsm.sv
-//
-// Written: Ross Thompson ross1728@gmail.com December 29, 2021
-// Modified:
-//
-// Purpose: Load/Store Unit's interface to BUS for cacheless system
-//
-// A component of the Wally configurable RISC-V project.
-//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// MIT LICENSE
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this
-// software and associated documentation files (the "Software"), to deal in the Software
-// without restriction, including without limitation the rights to use, copy, modify, merge,
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
-// to whom the Software is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or
-// substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
-// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
-// OR OTHER DEALINGS IN THE SOFTWARE.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`include "wally-config.vh"
-
-// HCLK and clk must be the same clock!
-module AHBBusfsm
- (input logic HCLK,
- input logic HRESETn,
-
- // IEU interface
- input logic [1:0] RW,
- input logic CPUBusy,
- output logic BusCommitted,
- output logic BusStall,
- output logic CaptureEn,
- input logic HREADY,
- output logic [1:0] HTRANS,
- output logic HWRITE
-);
-
- typedef enum logic [2:0] {STATE_READY,
- STATE_CAPTURE,
- STATE_DELAY,
- STATE_CPU_BUSY} busstatetype;
-
- typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype;
-
- (* mark_debug = "true" *) busstatetype BusCurrState, BusNextState;
-
- always_ff @(posedge HCLK)
- if (~HRESETn) BusCurrState <= #1 STATE_READY;
- else BusCurrState <= #1 BusNextState;
-
- always_comb begin
- case(BusCurrState)
- STATE_READY: if(HREADY & |RW) BusNextState = STATE_CAPTURE;
- else BusNextState = STATE_READY;
- STATE_CAPTURE: if(HREADY) BusNextState = STATE_DELAY;
- else BusNextState = STATE_CAPTURE;
- STATE_DELAY: if(CPUBusy) BusNextState = STATE_CPU_BUSY;
- else BusNextState = STATE_READY;
- STATE_CPU_BUSY: if(CPUBusy) BusNextState = STATE_CPU_BUSY;
- else BusNextState = STATE_READY;
- default: BusNextState = STATE_READY;
- endcase
- end
-
- assign BusStall = (BusCurrState == STATE_READY & |RW) |
- (BusCurrState == STATE_CAPTURE);
-
- assign BusCommitted = BusCurrState != STATE_READY;
-
- assign HTRANS = (BusCurrState == STATE_READY & HREADY & |RW) |
- (BusCurrState == STATE_CAPTURE & ~HREADY) ? AHB_NONSEQ : AHB_IDLE;
- assign HWRITE = (BusCurrState == STATE_READY) & RW[0]; // *** might not be necessary, maybe just RW[0]
- assign CaptureEn = BusCurrState == STATE_CAPTURE;
-
-endmodule