From d6c19e73f4f3c6dddfd95af02c0b69744e79e29e Mon Sep 17 00:00:00 2001
From: Ross Thompson <stephen.thompson.37@us.af.mil>
Date: Fri, 25 Jun 2021 11:00:42 -0500
Subject: [PATCH] Regression test runs further. The LSU state machine which
fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus
faults.
---
.../config/busybear/wally-config.vh | 3 +-
wally-pipelined/regression/wave.do | 134 ++++++++++++------
wally-pipelined/src/lsu/lsu.sv | 6 +-
3 files changed, 93 insertions(+), 50 deletions(-)
diff --git a/wally-pipelined/config/busybear/wally-config.vh b/wally-pipelined/config/busybear/wally-config.vh
index e6532ee51..0db13778e 100644
--- a/wally-pipelined/config/busybear/wally-config.vh
+++ b/wally-pipelined/config/busybear/wally-config.vh
@@ -30,8 +30,7 @@
`define BUILDROOT 0
`define BUSYBEAR 1
`define LINUX_FIX_READ {'h10000005}
-`define LINUX_TEST_VECTORS "../../../busybear_boot/"
-//`define LINUX_TEST_VECTORS "/courses/e190ax/busybear_boot/"
+`define LINUX_TEST_VECTORS "/courses/e190ax/busybear_boot/"
// RV32 or RV64: XLEN = 32 or 64
`define XLEN 64
diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do
index 88879334b..80edad360 100644
--- a/wally-pipelined/regression/wave.do
+++ b/wally-pipelined/regression/wave.do
@@ -7,37 +7,37 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/DataStall
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
-add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
-add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
-add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
-add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
-add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
-add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
-add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
-add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
-add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
-add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
+add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/DataStall
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
+add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
+add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD
+add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE
+add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM
+add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW
+add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/hart/StallF
+add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/hart/StallD
+add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/hart/StallE
+add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/hart/StallM
+add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/hart/StallW
add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
@@ -117,18 +117,18 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags
-add wave -noupdate -group alu -divider internals
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu
+add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a
+add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b
+add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
+add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/result
+add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/flags
+add wave -noupdate -expand -group alu -divider internals
+add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/overflow
+add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/carry
+add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero
+add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg
+add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt
+add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu
add wave -noupdate -group dcache -expand -group {cpu request} /testbench/dut/hart/MemAdrM
add wave -noupdate -group dcache -expand -group {cpu request} /testbench/dut/hart/WriteDataM
add wave -noupdate -group dcache /testbench/dut/hart/MemPAdrM
@@ -235,8 +235,52 @@ add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HADDRD
add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HSIZED
add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HWRITED
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/CurrState
+add wave -noupdate -expand -group lsu /testbench/dut/hart/arbiter/MemAdrM
+add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemPAdrM
+add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/DSquashBusAccessM
+add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HCLK
+add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HSELPLIC
+add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HADDR
+add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HWRITE
+add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HREADY
+add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HTRANS
+add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HWDATA
+add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/UARTIntr
+add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/GPIOIntr
+add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HREADPLIC
+add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HRESPPLIC
+add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HREADYPLIC
+add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/ExtIntM
+add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HCLK
+add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HSELGPIO
+add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HADDR
+add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HWDATA
+add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HWRITE
+add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADY
+add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HTRANS
+add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADGPIO
+add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HRESPGPIO
+add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADYGPIO
+add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsIn
+add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsOut
+add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsEn
+add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOIntr
+add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK
+add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT
+add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR
+add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWRITE
+add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWDATA
+add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADY
+add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HTRANS
+add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADCLINT
+add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HRESPCLINT
+add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADYCLINT
+add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME
+add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP
+add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM
+add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM
TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {32648010 ns} 0} {{Cursor 5} {4216 ns} 0}
+WaveRestoreCursors {{Cursor 4} {32648010 ns} 0} {{Cursor 5} {14425 ns} 0}
quietly wave cursor active 2
configure wave -namecolwidth 250
configure wave -valuecolwidth 189
@@ -252,4 +296,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
-WaveRestoreZoom {4167 ns} {4406 ns}
+WaveRestoreZoom {0 ns} {2330991 ns}
diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 096dd07c0..0ab4022c1 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -156,7 +156,7 @@ module lsu (
assign MemReadM = MemRWM[1] & ~NonBusTrapM & CurrState != STATE_STALLED;
assign MemWriteM = MemRWM[0] & ~NonBusTrapM && ~SquashSCM & CurrState != STATE_STALLED;
assign AtomicMaskedM = CurrState != STATE_STALLED ? AtomicM : 2'b00 ;
- assign MemAccessM = |MemRWM;
+ assign MemAccessM = MemReadM | MemWriteM;
// Determine if M stage committed
// Reset whenever unstalled. Set when access successfully occurs
@@ -195,7 +195,7 @@ module lsu (
endgenerate
// Data stall
- assign DataStall = (CurrState == STATE_FETCH) || (CurrState == STATE_FETCH_AMO);
+ assign DataStall = (NextState == STATE_FETCH) || (NextState == STATE_FETCH_AMO);
// Ross Thompson April 22, 2021
// for now we need to handle the issue where the data memory interface repeately
@@ -209,7 +209,7 @@ module lsu (
always_comb begin
case (CurrState)
- STATE_READY: if (MemRWM[1] & MemRWM[0]) NextState = STATE_FETCH_AMO; // *** should be some misalign check
+ STATE_READY: if (|AtomicMaskedM) NextState = STATE_FETCH_AMO; // *** should be some misalign check
else if (MemAccessM & ~DataMisalignedM) NextState = STATE_FETCH;
else NextState = STATE_READY;
STATE_FETCH_AMO: if (MemAckW) NextState = STATE_FETCH;