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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

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bbracker 2021-12-08 14:12:18 -08:00
commit d6ae6824ab
1 changed files with 13 additions and 1 deletions
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14
wally-pipelined/src/uncore/uart.sv
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@ -84,7 +84,19 @@ module uart (
logic BAUDOUTb; // loop tx clock BAUDOUTb back to rx clock RCLK logic BAUDOUTb; // loop tx clock BAUDOUTb back to rx clock RCLK
// *** make sure reads don't occur on UART unless fully selected because they could change state. This applies to all peripherals // *** make sure reads don't occur on UART unless fully selected because they could change state. This applies to all peripherals
uartPC16550D u(.RCLK(BAUDOUTb), .*); uartPC16550D u(
// Processor Interface
.HCLK, .HRESETn,
.A, .Din,
.Dout,
.MEMRb, .MEMWb,
.INTR, .TXRDYb, .RXRDYb,
// Clocks
.BAUDOUTb, .RCLK(BAUDOUTb),
// E1A Driver
.SIN, .DSRb, .DCDb, .CTSb, .RIb,
.SOUT, .RTSb, .DTRb, .OUT1b, .OUT2b
);
endmodule endmodule