mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-02 17:55:19 +00:00
Update formatting in an attempt to understand what's happening in this file
This commit is contained in:
Jordan Carlin
parent
017b3e9872
commit
d666a0dd7b
@ -35,37 +35,36 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
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localparam NUMREGS = P.E_SUPPORTED ? 16 : 32;
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// wally specific signals
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logic reset;
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logic clk;
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logic InstrValidD, InstrValidE;
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logic StallF, StallD;
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logic STATUS_SXL, STATUS_UXL;
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logic [P.XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, PCW;
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logic [31:0] InstrRawD, InstrRawE, InstrRawM, InstrRawW;
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logic InstrValidM, InstrValidW;
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logic StallE, StallM, StallW;
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logic FlushD, FlushE, FlushM, FlushW;
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logic TrapM, TrapW;
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logic HaltM, HaltW;
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logic [1:0] PrivilegeModeW;
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logic [P.XLEN-1:0] rf[NUMREGS];
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logic [NUMREGS-1:0] rf_wb;
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logic [4:0] rf_a3;
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logic rf_we3;
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logic [P.FLEN-1:0] frf[32];
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logic [`NUM_REGS-1:0] frf_wb;
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logic [4:0] frf_a4;
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logic frf_we4;
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logic [P.XLEN-1:0] CSRArray [4095:0];
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logic [P.XLEN-1:0] CSRArrayOld [4095:0];
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logic [`NUM_CSRS-1:0] CSR_W;
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logic CSRWriteM, CSRWriteW;
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logic [11:0] CSRAdrM, CSRAdrW;
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logic wfiM;
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logic InterruptM, InterruptW;
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logic reset;
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logic clk;
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logic InstrValidD, InstrValidE;
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logic StallF, StallD;
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logic STATUS_SXL, STATUS_UXL;
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logic [P.XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, PCW;
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logic [31:0] InstrRawD, InstrRawE, InstrRawM, InstrRawW;
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logic InstrValidM, InstrValidW;
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logic StallE, StallM, StallW;
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logic FlushD, FlushE, FlushM, FlushW;
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logic TrapM, TrapW;
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logic HaltM, HaltW;
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logic [1:0] PrivilegeModeW;
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logic [P.XLEN-1:0] rf[NUMREGS];
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logic [NUMREGS-1:0] rf_wb;
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logic [4:0] rf_a3;
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logic rf_we3;
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logic [P.FLEN-1:0] frf[32];
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logic [`NUM_REGS-1:0] frf_wb;
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logic [4:0] frf_a4;
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logic frf_we4;
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logic [P.XLEN-1:0] CSRArray [4095:0];
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logic [P.XLEN-1:0] CSRArrayOld [4095:0];
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logic [`NUM_CSRS-1:0] CSR_W;
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logic CSRWriteM, CSRWriteW;
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logic [11:0] CSRAdrM, CSRAdrW;
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logic wfiM;
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logic InterruptM, InterruptW;
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//For VM Verification
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logic [(P.XLEN-1):0] VAdrIM,VAdrDM,VAdrIW,VAdrDW;
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logic [(P.XLEN-1):0] PTE_iM,PTE_dM,PTE_iW,PTE_dW;
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logic [(P.PA_BITS-1):0] PAIM,PADM,PAIW,PADW;
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@ -73,7 +72,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
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logic ReadAccessM,WriteAccessM,ReadAccessW,WriteAccessW;
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logic ExecuteAccessF,ExecuteAccessD,ExecuteAccessE,ExecuteAccessM,ExecuteAccessW;
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assign clk = testbench.dut.clk;
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// assign InstrValidF = testbench.dut.core.ieu.InstrValidF; // not needed yet
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assign InstrValidD = testbench.dut.core.ieu.c.InstrValidD;
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@ -103,7 +101,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
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assign wfiM = testbench.dut.core.priv.priv.wfiM;
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assign InterruptM = testbench.dut.core.priv.priv.InterruptM;
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//FOr VM Verification
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//For VM Verification
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assign VAdrIM = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr;
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assign VAdrDM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.VAdr;
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assign PAIM = testbench.dut.core.ifu.immu.immu.PhysicalAddress;
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@ -116,21 +114,17 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
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assign PPN_iM = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN;
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assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN;
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logic valid;
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int csrid;
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always_comb begin
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// Since we are detected the CSR change by comparing the old value we need to
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// ensure the CSR is detected when the pipeline's Writeback stage is not
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// stalled. If it is stalled we want CSRArray to hold the old value.
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if(valid) begin
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// machine CSRs
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// *** missing PMP and performance counters.
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// Since we are detected the CSR change by comparing the old value we need to
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// ensure the CSR is detected when the pipeline's Writeback stage is not
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// stalled. If it is stalled we want CSRArray to hold the old value.
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if(valid) begin
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// machine CSRs
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// PMPCFG space is 0-15 3a0 - 3af
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int i, i4, i8, csrid;
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int i, i4, i8, csrid;
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logic [P.XLEN-1:0] pmp;
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for (i=0; i<P.PMP_ENTRIES; i+=8) begin
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i4 = i / 4;
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@ -157,134 +151,134 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
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CSRArray[csrid] = pmp;
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end
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CSRArray[12'h300] = testbench.dut.core.priv.priv.csr.csrm.MSTATUS_REGW;
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CSRArray[12'h305] = testbench.dut.core.priv.priv.csr.csrm.MTVEC_REGW;
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CSRArray[12'h341] = testbench.dut.core.priv.priv.csr.csrm.MEPC_REGW;
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CSRArray[12'h306] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW;
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CSRArray[12'h320] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW;
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CSRArray[12'h302] = testbench.dut.core.priv.priv.csr.csrm.MEDELEG_REGW;
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CSRArray[12'h303] = testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
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CSRArray[12'h344] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW;
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CSRArray[12'h304] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW;
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CSRArray[12'h301] = testbench.dut.core.priv.priv.csr.csrm.MISA_REGW;
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CSRArray[12'h30A] = testbench.dut.core.priv.priv.csr.csrm.MENVCFG_REGW;
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CSRArray[12'hF14] = testbench.dut.core.priv.priv.csr.csrm.MHARTID_REGW;
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CSRArray[12'h340] = testbench.dut.core.priv.priv.csr.csrm.MSCRATCH_REGW;
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CSRArray[12'h342] = testbench.dut.core.priv.priv.csr.csrm.MCAUSE_REGW;
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CSRArray[12'h343] = testbench.dut.core.priv.priv.csr.csrm.MTVAL_REGW;
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CSRArray[12'hF11] = 0;
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CSRArray[12'hF12] = 0;
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CSRArray[12'hF13] = {{P.XLEN-12{1'b0}}, 12'h100}; //P.XLEN'h100;
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CSRArray[12'hF15] = 0;
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CSRArray[12'h34A] = 0;
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// MCYCLE and MINSTRET
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CSRArray[12'hB00] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0];
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CSRArray[12'hB02] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
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// supervisor CSRs
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CSRArray[12'h100] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW;
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CSRArray[12'h104] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222;
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CSRArray[12'h105] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW;
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CSRArray[12'h141] = testbench.dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW;
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CSRArray[12'h106] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW;
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CSRArray[12'h10A] = testbench.dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW;
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CSRArray[12'h180] = testbench.dut.core.priv.priv.csr.csrs.csrs.SATP_REGW;
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CSRArray[12'h140] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW;
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CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW;
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CSRArray[12'h142] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW;
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CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
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CSRArray[12'h14D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[P.XLEN-1:0];
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// user CSRs
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CSRArray[12'h001] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW;
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CSRArray[12'h002] = testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW;
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CSRArray[12'h003] = {testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW};
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if (P.XLEN == 32) begin
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CSRArray[12'h310] = testbench.dut.core.priv.priv.csr.csrsr.MSTATUSH_REGW;
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CSRArray[12'h31A] = testbench.dut.core.priv.priv.csr.csrm.MENVCFGH_REGW;
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CSRArray[12'h15D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[63:32];
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end
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end else begin // hold the old value if the pipeline is stalled.
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CSRArray[12'h300] = testbench.dut.core.priv.priv.csr.csrm.MSTATUS_REGW;
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CSRArray[12'h305] = testbench.dut.core.priv.priv.csr.csrm.MTVEC_REGW;
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CSRArray[12'h341] = testbench.dut.core.priv.priv.csr.csrm.MEPC_REGW;
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CSRArray[12'h306] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW;
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CSRArray[12'h320] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW;
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CSRArray[12'h302] = testbench.dut.core.priv.priv.csr.csrm.MEDELEG_REGW;
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CSRArray[12'h303] = testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
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CSRArray[12'h344] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW;
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CSRArray[12'h304] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW;
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CSRArray[12'h301] = testbench.dut.core.priv.priv.csr.csrm.MISA_REGW;
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CSRArray[12'h30A] = testbench.dut.core.priv.priv.csr.csrm.MENVCFG_REGW;
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CSRArray[12'hF14] = testbench.dut.core.priv.priv.csr.csrm.MHARTID_REGW;
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CSRArray[12'h340] = testbench.dut.core.priv.priv.csr.csrm.MSCRATCH_REGW;
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CSRArray[12'h342] = testbench.dut.core.priv.priv.csr.csrm.MCAUSE_REGW;
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CSRArray[12'h343] = testbench.dut.core.priv.priv.csr.csrm.MTVAL_REGW;
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CSRArray[12'hF11] = 0;
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CSRArray[12'hF12] = 0;
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CSRArray[12'hF13] = {{P.XLEN-12{1'b0}}, 12'h100}; //P.XLEN'h100;
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CSRArray[12'hF15] = 0;
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CSRArray[12'h34A] = 0;
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// MCYCLE and MINSTRET
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CSRArray[12'hB00] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0];
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CSRArray[12'hB02] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
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// supervisor CSRs
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CSRArray[12'h100] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW;
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CSRArray[12'h104] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222;
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CSRArray[12'h105] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW;
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CSRArray[12'h141] = testbench.dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW;
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CSRArray[12'h106] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW;
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CSRArray[12'h10A] = testbench.dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW;
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CSRArray[12'h180] = testbench.dut.core.priv.priv.csr.csrs.csrs.SATP_REGW;
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CSRArray[12'h140] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW;
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CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW;
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CSRArray[12'h142] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW;
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CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
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CSRArray[12'h14D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[P.XLEN-1:0];
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// user CSRs
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CSRArray[12'h001] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW;
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CSRArray[12'h002] = testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW;
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CSRArray[12'h003] = {testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW};
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if (P.XLEN == 32) begin
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CSRArray[12'h310] = testbench.dut.core.priv.priv.csr.csrsr.MSTATUSH_REGW;
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CSRArray[12'h31A] = testbench.dut.core.priv.priv.csr.csrm.MENVCFGH_REGW;
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CSRArray[12'h15D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[63:32];
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end
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end else begin // hold the old value if the pipeline is stalled.
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// PMP CFG 3A0 to 3AF
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for(csrid='h3A0; csrid<='h3AF; csrid++)
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CSRArray[csrid] = CSRArrayOld[csrid];
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CSRArray[csrid] = CSRArrayOld[csrid];
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// PMP ADDR 3B0 to 3EF
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for(csrid='h3B0; csrid<='h3EF; csrid++)
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CSRArray[csrid] = CSRArrayOld[csrid];
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CSRArray[csrid] = CSRArrayOld[csrid];
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CSRArray[12'h300] = CSRArrayOld[12'h300];
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CSRArray[12'h305] = CSRArrayOld[12'h305];
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CSRArray[12'h341] = CSRArrayOld[12'h341];
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CSRArray[12'h306] = CSRArrayOld[12'h306];
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CSRArray[12'h320] = CSRArrayOld[12'h320];
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CSRArray[12'h302] = CSRArrayOld[12'h302];
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CSRArray[12'h303] = CSRArrayOld[12'h303];
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CSRArray[12'h344] = CSRArrayOld[12'h344];
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CSRArray[12'h304] = CSRArrayOld[12'h304];
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CSRArray[12'h301] = CSRArrayOld[12'h301];
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CSRArray[12'h30A] = CSRArrayOld[12'h30A];
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CSRArray[12'hF14] = CSRArrayOld[12'hF14];
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CSRArray[12'h340] = CSRArrayOld[12'h340];
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CSRArray[12'h342] = CSRArrayOld[12'h342];
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CSRArray[12'h343] = CSRArrayOld[12'h343];
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CSRArray[12'hF11] = CSRArrayOld[12'hF11];
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CSRArray[12'hF12] = CSRArrayOld[12'hF12];
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CSRArray[12'hF13] = CSRArrayOld[12'hF13];
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CSRArray[12'hF15] = CSRArrayOld[12'hF15];
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CSRArray[12'h34A] = CSRArrayOld[12'h34A];
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// MCYCLE and MINSTRET
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CSRArray[12'hB00] = CSRArrayOld[12'hB00];
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CSRArray[12'hB02] = CSRArrayOld[12'hB02];
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// supervisor CSRs
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CSRArray[12'h100] = CSRArrayOld[12'h100];
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CSRArray[12'h104] = CSRArrayOld[12'h104];
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CSRArray[12'h105] = CSRArrayOld[12'h105];
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CSRArray[12'h141] = CSRArrayOld[12'h141];
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CSRArray[12'h106] = CSRArrayOld[12'h106];
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CSRArray[12'h10A] = CSRArrayOld[12'h10A];
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CSRArray[12'h180] = CSRArrayOld[12'h180];
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CSRArray[12'h140] = CSRArrayOld[12'h140];
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CSRArray[12'h143] = CSRArrayOld[12'h143];
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CSRArray[12'h142] = CSRArrayOld[12'h142];
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CSRArray[12'h144] = CSRArrayOld[12'h144];
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CSRArray[12'h14D] = CSRArrayOld[12'h14D];
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// user CSRs
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CSRArray[12'h001] = CSRArrayOld[12'h001];
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CSRArray[12'h002] = CSRArrayOld[12'h002];
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CSRArray[12'h003] = CSRArrayOld[12'h003];
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if (P.XLEN == 32) begin
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CSRArray[12'h310] = CSRArrayOld[12'h310];
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CSRArray[12'h31A] = CSRArrayOld[12'h31A];
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CSRArray[12'h15D] = CSRArrayOld[12'h15D];
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CSRArray[12'h300] = CSRArrayOld[12'h300];
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CSRArray[12'h305] = CSRArrayOld[12'h305];
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CSRArray[12'h341] = CSRArrayOld[12'h341];
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CSRArray[12'h306] = CSRArrayOld[12'h306];
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CSRArray[12'h320] = CSRArrayOld[12'h320];
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CSRArray[12'h302] = CSRArrayOld[12'h302];
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CSRArray[12'h303] = CSRArrayOld[12'h303];
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CSRArray[12'h344] = CSRArrayOld[12'h344];
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CSRArray[12'h304] = CSRArrayOld[12'h304];
|
||||
CSRArray[12'h301] = CSRArrayOld[12'h301];
|
||||
CSRArray[12'h30A] = CSRArrayOld[12'h30A];
|
||||
CSRArray[12'hF14] = CSRArrayOld[12'hF14];
|
||||
CSRArray[12'h340] = CSRArrayOld[12'h340];
|
||||
CSRArray[12'h342] = CSRArrayOld[12'h342];
|
||||
CSRArray[12'h343] = CSRArrayOld[12'h343];
|
||||
CSRArray[12'hF11] = CSRArrayOld[12'hF11];
|
||||
CSRArray[12'hF12] = CSRArrayOld[12'hF12];
|
||||
CSRArray[12'hF13] = CSRArrayOld[12'hF13];
|
||||
CSRArray[12'hF15] = CSRArrayOld[12'hF15];
|
||||
CSRArray[12'h34A] = CSRArrayOld[12'h34A];
|
||||
// MCYCLE and MINSTRET
|
||||
CSRArray[12'hB00] = CSRArrayOld[12'hB00];
|
||||
CSRArray[12'hB02] = CSRArrayOld[12'hB02];
|
||||
// supervisor CSRs
|
||||
CSRArray[12'h100] = CSRArrayOld[12'h100];
|
||||
CSRArray[12'h104] = CSRArrayOld[12'h104];
|
||||
CSRArray[12'h105] = CSRArrayOld[12'h105];
|
||||
CSRArray[12'h141] = CSRArrayOld[12'h141];
|
||||
CSRArray[12'h106] = CSRArrayOld[12'h106];
|
||||
CSRArray[12'h10A] = CSRArrayOld[12'h10A];
|
||||
CSRArray[12'h180] = CSRArrayOld[12'h180];
|
||||
CSRArray[12'h140] = CSRArrayOld[12'h140];
|
||||
CSRArray[12'h143] = CSRArrayOld[12'h143];
|
||||
CSRArray[12'h142] = CSRArrayOld[12'h142];
|
||||
CSRArray[12'h144] = CSRArrayOld[12'h144];
|
||||
CSRArray[12'h14D] = CSRArrayOld[12'h14D];
|
||||
// user CSRs
|
||||
CSRArray[12'h001] = CSRArrayOld[12'h001];
|
||||
CSRArray[12'h002] = CSRArrayOld[12'h002];
|
||||
CSRArray[12'h003] = CSRArrayOld[12'h003];
|
||||
|
||||
if (P.XLEN == 32) begin
|
||||
CSRArray[12'h310] = CSRArrayOld[12'h310];
|
||||
CSRArray[12'h31A] = CSRArrayOld[12'h31A];
|
||||
CSRArray[12'h15D] = CSRArrayOld[12'h15D];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
genvar index;
|
||||
assign rf[0] = 0;
|
||||
for(index = 1; index < NUMREGS; index += 1)
|
||||
assign rf[index] = testbench.dut.core.ieu.dp.regf.rf[index];
|
||||
assign rf[index] = testbench.dut.core.ieu.dp.regf.rf[index];
|
||||
|
||||
assign rf_a3 = testbench.dut.core.ieu.dp.regf.a3;
|
||||
assign rf_we3 = testbench.dut.core.ieu.dp.regf.we3;
|
||||
|
||||
always_comb begin
|
||||
rf_wb <= 0;
|
||||
if(rf_we3)
|
||||
rf_wb[rf_a3] <= 1'b1;
|
||||
rf_wb <= 0;
|
||||
if(rf_we3)
|
||||
rf_wb[rf_a3] <= 1'b1;
|
||||
end
|
||||
|
||||
for(index = 0; index < NUMREGS; index += 1)
|
||||
assign frf[index] = testbench.dut.core.fpu.fpu.fregfile.rf[index];
|
||||
assign frf[index] = testbench.dut.core.fpu.fpu.fregfile.rf[index];
|
||||
|
||||
assign frf_a4 = testbench.dut.core.fpu.fpu.fregfile.a4;
|
||||
assign frf_we4 = testbench.dut.core.fpu.fpu.fregfile.we4;
|
||||
|
||||
always_comb begin
|
||||
frf_wb <= 0;
|
||||
if(frf_we4)
|
||||
frf_wb[frf_a4] <= 1'b1;
|
||||
frf_wb <= 0;
|
||||
if(frf_we4)
|
||||
frf_wb[frf_a4] <= 1'b1;
|
||||
end
|
||||
|
||||
assign CSRAdrM = testbench.dut.core.priv.priv.csr.CSRAdrM;
|
||||
@ -333,17 +327,17 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
|
||||
assign rvvi.intr[0][0] = InterruptW;
|
||||
assign rvvi.mode[0][0] = PrivilegeModeW;
|
||||
assign rvvi.ixl[0][0] = PrivilegeModeW == 2'b11 ? 2'b10 :
|
||||
PrivilegeModeW == 2'b01 ? STATUS_SXL : STATUS_UXL;
|
||||
PrivilegeModeW == 2'b01 ? STATUS_SXL : STATUS_UXL;
|
||||
assign rvvi.pc_wdata[0][0] = ~FlushW ? PCM :
|
||||
~FlushM ? PCE :
|
||||
~FlushE ? PCD :
|
||||
~FlushD ? PCF : PCNextF;
|
||||
~FlushM ? PCE :
|
||||
~FlushE ? PCD :
|
||||
~FlushD ? PCF : PCNextF;
|
||||
|
||||
for(index = 0; index < `NUM_REGS; index += 1) begin
|
||||
assign rvvi.x_wdata[0][0][index] = rf[index];
|
||||
assign rvvi.x_wb[0][0][index] = rf_wb[index];
|
||||
assign rvvi.f_wdata[0][0][index] = frf[index];
|
||||
assign rvvi.f_wb[0][0][index] = frf_wb[index];
|
||||
assign rvvi.x_wdata[0][0][index] = rf[index];
|
||||
assign rvvi.x_wb[0][0][index] = rf_wb[index];
|
||||
assign rvvi.f_wdata[0][0][index] = frf[index];
|
||||
assign rvvi.f_wb[0][0][index] = frf_wb[index];
|
||||
end
|
||||
|
||||
// record previous csr value.
|
||||
@ -389,6 +383,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
|
||||
CSRArrayOld[12'h001] = CSRArray[12'h001];
|
||||
CSRArrayOld[12'h002] = CSRArray[12'h002];
|
||||
CSRArrayOld[12'h003] = CSRArray[12'h003];
|
||||
|
||||
if (P.XLEN == 32) begin
|
||||
CSRArrayOld[12'h310] = CSRArray[12'h310];
|
||||
CSRArrayOld[12'h31A] = CSRArray[12'h31A];
|
||||
@ -442,6 +437,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
|
||||
assign CSR_W[12'h001] = (CSRArrayOld[12'h001] != CSRArray[12'h001]) ? 1 : 0;
|
||||
assign CSR_W[12'h002] = (CSRArrayOld[12'h002] != CSRArray[12'h002]) ? 1 : 0;
|
||||
assign CSR_W[12'h003] = (CSRArrayOld[12'h003] != CSRArray[12'h003]) ? 1 : 0;
|
||||
|
||||
if (P.XLEN == 32) begin
|
||||
assign CSR_W[12'h310] = (CSRArrayOld[12'h310] != CSRArray[12'h310]) ? 1 : 0;
|
||||
assign CSR_W[12'h31A] = (CSRArrayOld[12'h31A] != CSRArray[12'h31A]) ? 1 : 0;
|
||||
@ -485,6 +481,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
|
||||
assign rvvi.csr_wb[0][0][12'h001] = CSR_W[12'h001];
|
||||
assign rvvi.csr_wb[0][0][12'h002] = CSR_W[12'h002];
|
||||
assign rvvi.csr_wb[0][0][12'h003] = CSR_W[12'h003];
|
||||
|
||||
if (P.XLEN == 32) begin
|
||||
assign rvvi.csr_wb[0][0][12'h310] = CSR_W[12'h310];
|
||||
assign rvvi.csr_wb[0][0][12'h31A] = CSR_W[12'h31A];
|
||||
@ -528,6 +525,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
|
||||
assign rvvi.csr[0][0][12'h001] = CSRArray[12'h001];
|
||||
assign rvvi.csr[0][0][12'h002] = CSRArray[12'h002];
|
||||
assign rvvi.csr[0][0][12'h003] = CSRArray[12'h003];
|
||||
|
||||
if (P.XLEN == 32) begin
|
||||
assign rvvi.csr[0][0][12'h310] = CSRArray[12'h310];
|
||||
assign rvvi.csr[0][0][12'h31A] = CSRArray[12'h31A];
|
||||
@ -565,49 +563,49 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if(rvvi.valid[0][0]) begin
|
||||
if(`STD_LOG) begin
|
||||
$fwrite(file, "%016x, %08x, %s\t\t", rvvi.pc_rdata[0][0], rvvi.insn[0][0], instrWName);
|
||||
for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
|
||||
if(rvvi.x_wb[0][0][index2]) begin
|
||||
$fwrite(file, "rf[%02d] = %016x ", index2, rvvi.x_wdata[0][0][index2]);
|
||||
end
|
||||
if(rvvi.valid[0][0]) begin
|
||||
if(`STD_LOG) begin
|
||||
$fwrite(file, "%016x, %08x, %s\t\t", rvvi.pc_rdata[0][0], rvvi.insn[0][0], instrWName);
|
||||
for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
|
||||
if(rvvi.x_wb[0][0][index2]) begin
|
||||
$fwrite(file, "rf[%02d] = %016x ", index2, rvvi.x_wdata[0][0][index2]);
|
||||
end
|
||||
for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
|
||||
if(rvvi.f_wb[0][0][index2]) begin
|
||||
$fwrite(file, "frf[%02d] = %016x ", index2, rvvi.f_wdata[0][0][index2]);
|
||||
end
|
||||
end
|
||||
for(index2 = 0; index2 < `NUM_CSRS; index2 += 1) begin
|
||||
if(rvvi.csr_wb[0][0][index2]) begin
|
||||
$fwrite(file, "csr[%03x] = %016x ", index2, rvvi.csr[0][0][index2]);
|
||||
end
|
||||
end
|
||||
$fwrite(file, "\n");
|
||||
end
|
||||
if(`PRINT_PC_INSTR & !(`PRINT_ALL | `PRINT_MOST))
|
||||
$display("order = %08d, PC = %08x, insn = %08x", rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0]);
|
||||
else if(`PRINT_MOST & !`PRINT_ALL)
|
||||
$display("order = %08d, PC = %010x, insn = %08x, trap = %1d, halt = %1d, intr = %1d, mode = %1x, ixl = %1x, pc_wdata = %010x, x%02d = %016x, f%02d = %016x, csr%03x = %016x",
|
||||
rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0], rvvi.trap[0][0], rvvi.halt[0][0], rvvi.intr[0][0], rvvi.mode[0][0], rvvi.ixl[0][0], rvvi.pc_wdata[0][0], rf_a3, rvvi.x_wdata[0][0][rf_a3], frf_a4, rvvi.f_wdata[0][0][frf_a4], CSRAdrW, rvvi.csr[0][0][CSRAdrW]);
|
||||
else if(`PRINT_ALL) begin
|
||||
$display("order = %08d, PC = %08x, insn = %08x, trap = %1d, halt = %1d, intr = %1d, mode = %1x, ixl = %1x, pc_wdata = %08x",
|
||||
rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0], rvvi.trap[0][0], rvvi.halt[0][0], rvvi.intr[0][0], rvvi.mode[0][0], rvvi.ixl[0][0], rvvi.pc_wdata[0][0]);
|
||||
for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
|
||||
$display("x%02d = %08x", index2, rvvi.x_wdata[0][0][index2]);
|
||||
end
|
||||
for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
|
||||
$display("f%02d = %08x", index2, rvvi.f_wdata[0][0][index2]);
|
||||
end
|
||||
end
|
||||
if (`PRINT_CSRS) begin
|
||||
for(index2 = 0; index2 < `NUM_CSRS; index2 += 1) begin
|
||||
if(CSR_W[index2]) begin
|
||||
$display("%t: CSR %03x = %x", $time(), index2, CSRArray[index2]);
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
|
||||
if(rvvi.f_wb[0][0][index2]) begin
|
||||
$fwrite(file, "frf[%02d] = %016x ", index2, rvvi.f_wdata[0][0][index2]);
|
||||
end
|
||||
end
|
||||
for(index2 = 0; index2 < `NUM_CSRS; index2 += 1) begin
|
||||
if(rvvi.csr_wb[0][0][index2]) begin
|
||||
$fwrite(file, "csr[%03x] = %016x ", index2, rvvi.csr[0][0][index2]);
|
||||
end
|
||||
end
|
||||
$fwrite(file, "\n");
|
||||
end
|
||||
if(`PRINT_PC_INSTR & !(`PRINT_ALL | `PRINT_MOST))
|
||||
$display("order = %08d, PC = %08x, insn = %08x", rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0]);
|
||||
else if(`PRINT_MOST & !`PRINT_ALL)
|
||||
$display("order = %08d, PC = %010x, insn = %08x, trap = %1d, halt = %1d, intr = %1d, mode = %1x, ixl = %1x, pc_wdata = %010x, x%02d = %016x, f%02d = %016x, csr%03x = %016x",
|
||||
rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0], rvvi.trap[0][0], rvvi.halt[0][0], rvvi.intr[0][0], rvvi.mode[0][0], rvvi.ixl[0][0], rvvi.pc_wdata[0][0], rf_a3, rvvi.x_wdata[0][0][rf_a3], frf_a4, rvvi.f_wdata[0][0][frf_a4], CSRAdrW, rvvi.csr[0][0][CSRAdrW]);
|
||||
else if(`PRINT_ALL) begin
|
||||
$display("order = %08d, PC = %08x, insn = %08x, trap = %1d, halt = %1d, intr = %1d, mode = %1x, ixl = %1x, pc_wdata = %08x",
|
||||
rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0], rvvi.trap[0][0], rvvi.halt[0][0], rvvi.intr[0][0], rvvi.mode[0][0], rvvi.ixl[0][0], rvvi.pc_wdata[0][0]);
|
||||
for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
|
||||
$display("x%02d = %08x", index2, rvvi.x_wdata[0][0][index2]);
|
||||
end
|
||||
for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
|
||||
$display("f%02d = %08x", index2, rvvi.f_wdata[0][0][index2]);
|
||||
end
|
||||
end
|
||||
if (`PRINT_CSRS) begin
|
||||
for(index2 = 0; index2 < `NUM_CSRS; index2 += 1) begin
|
||||
if(CSR_W[index2]) begin
|
||||
$display("%t: CSR %03x = %x", $time(), index2, CSRArray[index2]);
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
if(HaltW) $finish;
|
||||
end
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user