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Update formatting in an attempt to understand what's happening in this file

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Jordan Carlin 2024-11-13 18:26:53 -08:00
parent 017b3e9872
commit d666a0dd7b
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1 changed files with 193 additions and 195 deletions
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testbench/common/wallyTracer.sv
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@ -35,37 +35,36 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
localparam NUMREGS = P.E_SUPPORTED ? 16 : 32; localparam NUMREGS = P.E_SUPPORTED ? 16 : 32;
// wally specific signals // wally specific signals
logic reset; logic reset;
logic clk; logic clk;
logic InstrValidD, InstrValidE; logic InstrValidD, InstrValidE;
logic StallF, StallD; logic StallF, StallD;
logic STATUS_SXL, STATUS_UXL; logic STATUS_SXL, STATUS_UXL;
logic [P.XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, PCW; logic [P.XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, PCW;
logic [31:0] InstrRawD, InstrRawE, InstrRawM, InstrRawW; logic [31:0] InstrRawD, InstrRawE, InstrRawM, InstrRawW;
logic InstrValidM, InstrValidW; logic InstrValidM, InstrValidW;
logic StallE, StallM, StallW; logic StallE, StallM, StallW;
logic FlushD, FlushE, FlushM, FlushW; logic FlushD, FlushE, FlushM, FlushW;
logic TrapM, TrapW; logic TrapM, TrapW;
logic HaltM, HaltW; logic HaltM, HaltW;
logic [1:0] PrivilegeModeW; logic [1:0] PrivilegeModeW;
logic [P.XLEN-1:0] rf[NUMREGS]; logic [P.XLEN-1:0] rf[NUMREGS];
logic [NUMREGS-1:0] rf_wb; logic [NUMREGS-1:0] rf_wb;
logic [4:0] rf_a3; logic [4:0] rf_a3;
logic rf_we3; logic rf_we3;
logic [P.FLEN-1:0] frf[32]; logic [P.FLEN-1:0] frf[32];
logic [`NUM_REGS-1:0] frf_wb; logic [`NUM_REGS-1:0] frf_wb;
logic [4:0] frf_a4; logic [4:0] frf_a4;
logic frf_we4; logic frf_we4;
logic [P.XLEN-1:0] CSRArray [4095:0]; logic [P.XLEN-1:0] CSRArray [4095:0];
logic [P.XLEN-1:0] CSRArrayOld [4095:0]; logic [P.XLEN-1:0] CSRArrayOld [4095:0];
logic [`NUM_CSRS-1:0] CSR_W; logic [`NUM_CSRS-1:0] CSR_W;
logic CSRWriteM, CSRWriteW; logic CSRWriteM, CSRWriteW;
logic [11:0] CSRAdrM, CSRAdrW; logic [11:0] CSRAdrM, CSRAdrW;
logic wfiM; logic wfiM;
logic InterruptM, InterruptW; logic InterruptM, InterruptW;
//For VM Verification //For VM Verification
logic [(P.XLEN-1):0] VAdrIM,VAdrDM,VAdrIW,VAdrDW; logic [(P.XLEN-1):0] VAdrIM,VAdrDM,VAdrIW,VAdrDW;
logic [(P.XLEN-1):0] PTE_iM,PTE_dM,PTE_iW,PTE_dW; logic [(P.XLEN-1):0] PTE_iM,PTE_dM,PTE_iW,PTE_dW;
logic [(P.PA_BITS-1):0] PAIM,PADM,PAIW,PADW; logic [(P.PA_BITS-1):0] PAIM,PADM,PAIW,PADW;
@ -73,7 +72,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
logic ReadAccessM,WriteAccessM,ReadAccessW,WriteAccessW; logic ReadAccessM,WriteAccessM,ReadAccessW,WriteAccessW;
logic ExecuteAccessF,ExecuteAccessD,ExecuteAccessE,ExecuteAccessM,ExecuteAccessW; logic ExecuteAccessF,ExecuteAccessD,ExecuteAccessE,ExecuteAccessM,ExecuteAccessW;
assign clk = testbench.dut.clk; assign clk = testbench.dut.clk;
// assign InstrValidF = testbench.dut.core.ieu.InstrValidF; // not needed yet // assign InstrValidF = testbench.dut.core.ieu.InstrValidF; // not needed yet
assign InstrValidD = testbench.dut.core.ieu.c.InstrValidD; assign InstrValidD = testbench.dut.core.ieu.c.InstrValidD;
@ -103,7 +101,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
assign wfiM = testbench.dut.core.priv.priv.wfiM; assign wfiM = testbench.dut.core.priv.priv.wfiM;
assign InterruptM = testbench.dut.core.priv.priv.InterruptM; assign InterruptM = testbench.dut.core.priv.priv.InterruptM;
//FOr VM Verification //For VM Verification
assign VAdrIM = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr; assign VAdrIM = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr;
assign VAdrDM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.VAdr; assign VAdrDM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.VAdr;
assign PAIM = testbench.dut.core.ifu.immu.immu.PhysicalAddress; assign PAIM = testbench.dut.core.ifu.immu.immu.PhysicalAddress;
@ -116,21 +114,17 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
assign PPN_iM = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN; assign PPN_iM = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN;
assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN;
logic valid; logic valid;
int csrid; int csrid;
always_comb begin always_comb begin
// Since we are detected the CSR change by comparing the old value we need to // Since we are detected the CSR change by comparing the old value we need to
// ensure the CSR is detected when the pipeline's Writeback stage is not // ensure the CSR is detected when the pipeline's Writeback stage is not
// stalled. If it is stalled we want CSRArray to hold the old value. // stalled. If it is stalled we want CSRArray to hold the old value.
if(valid) begin if(valid) begin
// machine CSRs // machine CSRs
// *** missing PMP and performance counters.
// PMPCFG space is 0-15 3a0 - 3af // PMPCFG space is 0-15 3a0 - 3af
int i, i4, i8, csrid; int i, i4, i8, csrid;
logic [P.XLEN-1:0] pmp; logic [P.XLEN-1:0] pmp;
for (i=0; i<P.PMP_ENTRIES; i+=8) begin for (i=0; i<P.PMP_ENTRIES; i+=8) begin
i4 = i / 4; i4 = i / 4;
@ -157,134 +151,134 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
CSRArray[csrid] = pmp; CSRArray[csrid] = pmp;
end end
CSRArray[12'h300] = testbench.dut.core.priv.priv.csr.csrm.MSTATUS_REGW; CSRArray[12'h300] = testbench.dut.core.priv.priv.csr.csrm.MSTATUS_REGW;
CSRArray[12'h305] = testbench.dut.core.priv.priv.csr.csrm.MTVEC_REGW; CSRArray[12'h305] = testbench.dut.core.priv.priv.csr.csrm.MTVEC_REGW;
CSRArray[12'h341] = testbench.dut.core.priv.priv.csr.csrm.MEPC_REGW; CSRArray[12'h341] = testbench.dut.core.priv.priv.csr.csrm.MEPC_REGW;
CSRArray[12'h306] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW; CSRArray[12'h306] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW;
CSRArray[12'h320] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW; CSRArray[12'h320] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW;
CSRArray[12'h302] = testbench.dut.core.priv.priv.csr.csrm.MEDELEG_REGW; CSRArray[12'h302] = testbench.dut.core.priv.priv.csr.csrm.MEDELEG_REGW;
CSRArray[12'h303] = testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW; CSRArray[12'h303] = testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
CSRArray[12'h344] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW; CSRArray[12'h344] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW;
CSRArray[12'h304] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW; CSRArray[12'h304] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW;
CSRArray[12'h301] = testbench.dut.core.priv.priv.csr.csrm.MISA_REGW; CSRArray[12'h301] = testbench.dut.core.priv.priv.csr.csrm.MISA_REGW;
CSRArray[12'h30A] = testbench.dut.core.priv.priv.csr.csrm.MENVCFG_REGW; CSRArray[12'h30A] = testbench.dut.core.priv.priv.csr.csrm.MENVCFG_REGW;
CSRArray[12'hF14] = testbench.dut.core.priv.priv.csr.csrm.MHARTID_REGW; CSRArray[12'hF14] = testbench.dut.core.priv.priv.csr.csrm.MHARTID_REGW;
CSRArray[12'h340] = testbench.dut.core.priv.priv.csr.csrm.MSCRATCH_REGW; CSRArray[12'h340] = testbench.dut.core.priv.priv.csr.csrm.MSCRATCH_REGW;
CSRArray[12'h342] = testbench.dut.core.priv.priv.csr.csrm.MCAUSE_REGW; CSRArray[12'h342] = testbench.dut.core.priv.priv.csr.csrm.MCAUSE_REGW;
CSRArray[12'h343] = testbench.dut.core.priv.priv.csr.csrm.MTVAL_REGW; CSRArray[12'h343] = testbench.dut.core.priv.priv.csr.csrm.MTVAL_REGW;
CSRArray[12'hF11] = 0; CSRArray[12'hF11] = 0;
CSRArray[12'hF12] = 0; CSRArray[12'hF12] = 0;
CSRArray[12'hF13] = {{P.XLEN-12{1'b0}}, 12'h100}; //P.XLEN'h100; CSRArray[12'hF13] = {{P.XLEN-12{1'b0}}, 12'h100}; //P.XLEN'h100;
CSRArray[12'hF15] = 0; CSRArray[12'hF15] = 0;
CSRArray[12'h34A] = 0; CSRArray[12'h34A] = 0;
// MCYCLE and MINSTRET // MCYCLE and MINSTRET
CSRArray[12'hB00] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0]; CSRArray[12'hB00] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0];
CSRArray[12'hB02] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]; CSRArray[12'hB02] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
// supervisor CSRs // supervisor CSRs
CSRArray[12'h100] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW; CSRArray[12'h100] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW;
CSRArray[12'h104] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222; CSRArray[12'h104] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222;
CSRArray[12'h105] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW; CSRArray[12'h105] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW;
CSRArray[12'h141] = testbench.dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW; CSRArray[12'h141] = testbench.dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW;
CSRArray[12'h106] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW; CSRArray[12'h106] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW;
CSRArray[12'h10A] = testbench.dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW; CSRArray[12'h10A] = testbench.dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW;
CSRArray[12'h180] = testbench.dut.core.priv.priv.csr.csrs.csrs.SATP_REGW; CSRArray[12'h180] = testbench.dut.core.priv.priv.csr.csrs.csrs.SATP_REGW;
CSRArray[12'h140] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW; CSRArray[12'h140] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW;
CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW; CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW;
CSRArray[12'h142] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; CSRArray[12'h142] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW;
CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW; CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
CSRArray[12'h14D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[P.XLEN-1:0]; CSRArray[12'h14D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[P.XLEN-1:0];
// user CSRs // user CSRs
CSRArray[12'h001] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW; CSRArray[12'h001] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW;
CSRArray[12'h002] = testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW; CSRArray[12'h002] = testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW;
CSRArray[12'h003] = {testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; CSRArray[12'h003] = {testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW};
if (P.XLEN == 32) begin
CSRArray[12'h310] = testbench.dut.core.priv.priv.csr.csrsr.MSTATUSH_REGW;
CSRArray[12'h31A] = testbench.dut.core.priv.priv.csr.csrm.MENVCFGH_REGW;
CSRArray[12'h15D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[63:32];
end
end else begin // hold the old value if the pipeline is stalled.
if (P.XLEN == 32) begin
CSRArray[12'h310] = testbench.dut.core.priv.priv.csr.csrsr.MSTATUSH_REGW;
CSRArray[12'h31A] = testbench.dut.core.priv.priv.csr.csrm.MENVCFGH_REGW;
CSRArray[12'h15D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[63:32];
end
end else begin // hold the old value if the pipeline is stalled.
// PMP CFG 3A0 to 3AF // PMP CFG 3A0 to 3AF
for(csrid='h3A0; csrid<='h3AF; csrid++) for(csrid='h3A0; csrid<='h3AF; csrid++)
CSRArray[csrid] = CSRArrayOld[csrid]; CSRArray[csrid] = CSRArrayOld[csrid];
// PMP ADDR 3B0 to 3EF // PMP ADDR 3B0 to 3EF
for(csrid='h3B0; csrid<='h3EF; csrid++) for(csrid='h3B0; csrid<='h3EF; csrid++)
CSRArray[csrid] = CSRArrayOld[csrid]; CSRArray[csrid] = CSRArrayOld[csrid];
CSRArray[12'h300] = CSRArrayOld[12'h300]; CSRArray[12'h300] = CSRArrayOld[12'h300];
CSRArray[12'h305] = CSRArrayOld[12'h305]; CSRArray[12'h305] = CSRArrayOld[12'h305];
CSRArray[12'h341] = CSRArrayOld[12'h341]; CSRArray[12'h341] = CSRArrayOld[12'h341];
CSRArray[12'h306] = CSRArrayOld[12'h306]; CSRArray[12'h306] = CSRArrayOld[12'h306];
CSRArray[12'h320] = CSRArrayOld[12'h320]; CSRArray[12'h320] = CSRArrayOld[12'h320];
CSRArray[12'h302] = CSRArrayOld[12'h302]; CSRArray[12'h302] = CSRArrayOld[12'h302];
CSRArray[12'h303] = CSRArrayOld[12'h303]; CSRArray[12'h303] = CSRArrayOld[12'h303];
CSRArray[12'h344] = CSRArrayOld[12'h344]; CSRArray[12'h344] = CSRArrayOld[12'h344];
CSRArray[12'h304] = CSRArrayOld[12'h304]; CSRArray[12'h304] = CSRArrayOld[12'h304];
CSRArray[12'h301] = CSRArrayOld[12'h301]; CSRArray[12'h301] = CSRArrayOld[12'h301];
CSRArray[12'h30A] = CSRArrayOld[12'h30A]; CSRArray[12'h30A] = CSRArrayOld[12'h30A];
CSRArray[12'hF14] = CSRArrayOld[12'hF14]; CSRArray[12'hF14] = CSRArrayOld[12'hF14];
CSRArray[12'h340] = CSRArrayOld[12'h340]; CSRArray[12'h340] = CSRArrayOld[12'h340];
CSRArray[12'h342] = CSRArrayOld[12'h342]; CSRArray[12'h342] = CSRArrayOld[12'h342];
CSRArray[12'h343] = CSRArrayOld[12'h343]; CSRArray[12'h343] = CSRArrayOld[12'h343];
CSRArray[12'hF11] = CSRArrayOld[12'hF11]; CSRArray[12'hF11] = CSRArrayOld[12'hF11];
CSRArray[12'hF12] = CSRArrayOld[12'hF12]; CSRArray[12'hF12] = CSRArrayOld[12'hF12];
CSRArray[12'hF13] = CSRArrayOld[12'hF13]; CSRArray[12'hF13] = CSRArrayOld[12'hF13];
CSRArray[12'hF15] = CSRArrayOld[12'hF15]; CSRArray[12'hF15] = CSRArrayOld[12'hF15];
CSRArray[12'h34A] = CSRArrayOld[12'h34A]; CSRArray[12'h34A] = CSRArrayOld[12'h34A];
// MCYCLE and MINSTRET // MCYCLE and MINSTRET
CSRArray[12'hB00] = CSRArrayOld[12'hB00]; CSRArray[12'hB00] = CSRArrayOld[12'hB00];
CSRArray[12'hB02] = CSRArrayOld[12'hB02]; CSRArray[12'hB02] = CSRArrayOld[12'hB02];
// supervisor CSRs // supervisor CSRs
CSRArray[12'h100] = CSRArrayOld[12'h100]; CSRArray[12'h100] = CSRArrayOld[12'h100];
CSRArray[12'h104] = CSRArrayOld[12'h104]; CSRArray[12'h104] = CSRArrayOld[12'h104];
CSRArray[12'h105] = CSRArrayOld[12'h105]; CSRArray[12'h105] = CSRArrayOld[12'h105];
CSRArray[12'h141] = CSRArrayOld[12'h141]; CSRArray[12'h141] = CSRArrayOld[12'h141];
CSRArray[12'h106] = CSRArrayOld[12'h106]; CSRArray[12'h106] = CSRArrayOld[12'h106];
CSRArray[12'h10A] = CSRArrayOld[12'h10A]; CSRArray[12'h10A] = CSRArrayOld[12'h10A];
CSRArray[12'h180] = CSRArrayOld[12'h180]; CSRArray[12'h180] = CSRArrayOld[12'h180];
CSRArray[12'h140] = CSRArrayOld[12'h140]; CSRArray[12'h140] = CSRArrayOld[12'h140];
CSRArray[12'h143] = CSRArrayOld[12'h143]; CSRArray[12'h143] = CSRArrayOld[12'h143];
CSRArray[12'h142] = CSRArrayOld[12'h142]; CSRArray[12'h142] = CSRArrayOld[12'h142];
CSRArray[12'h144] = CSRArrayOld[12'h144]; CSRArray[12'h144] = CSRArrayOld[12'h144];
CSRArray[12'h14D] = CSRArrayOld[12'h14D]; CSRArray[12'h14D] = CSRArrayOld[12'h14D];
// user CSRs // user CSRs
CSRArray[12'h001] = CSRArrayOld[12'h001]; CSRArray[12'h001] = CSRArrayOld[12'h001];
CSRArray[12'h002] = CSRArrayOld[12'h002]; CSRArray[12'h002] = CSRArrayOld[12'h002];
CSRArray[12'h003] = CSRArrayOld[12'h003]; CSRArray[12'h003] = CSRArrayOld[12'h003];
if (P.XLEN == 32) begin
CSRArray[12'h310] = CSRArrayOld[12'h310]; if (P.XLEN == 32) begin
CSRArray[12'h31A] = CSRArrayOld[12'h31A]; CSRArray[12'h310] = CSRArrayOld[12'h310];
CSRArray[12'h15D] = CSRArrayOld[12'h15D]; CSRArray[12'h31A] = CSRArrayOld[12'h31A];
CSRArray[12'h15D] = CSRArrayOld[12'h15D];
end
end end
end
end end
genvar index; genvar index;
assign rf[0] = 0; assign rf[0] = 0;
for(index = 1; index < NUMREGS; index += 1) for(index = 1; index < NUMREGS; index += 1)
assign rf[index] = testbench.dut.core.ieu.dp.regf.rf[index]; assign rf[index] = testbench.dut.core.ieu.dp.regf.rf[index];
assign rf_a3 = testbench.dut.core.ieu.dp.regf.a3; assign rf_a3 = testbench.dut.core.ieu.dp.regf.a3;
assign rf_we3 = testbench.dut.core.ieu.dp.regf.we3; assign rf_we3 = testbench.dut.core.ieu.dp.regf.we3;
always_comb begin always_comb begin
rf_wb <= 0; rf_wb <= 0;
if(rf_we3) if(rf_we3)
rf_wb[rf_a3] <= 1'b1; rf_wb[rf_a3] <= 1'b1;
end end
for(index = 0; index < NUMREGS; index += 1) for(index = 0; index < NUMREGS; index += 1)
assign frf[index] = testbench.dut.core.fpu.fpu.fregfile.rf[index]; assign frf[index] = testbench.dut.core.fpu.fpu.fregfile.rf[index];
assign frf_a4 = testbench.dut.core.fpu.fpu.fregfile.a4; assign frf_a4 = testbench.dut.core.fpu.fpu.fregfile.a4;
assign frf_we4 = testbench.dut.core.fpu.fpu.fregfile.we4; assign frf_we4 = testbench.dut.core.fpu.fpu.fregfile.we4;
always_comb begin always_comb begin
frf_wb <= 0; frf_wb <= 0;
if(frf_we4) if(frf_we4)
frf_wb[frf_a4] <= 1'b1; frf_wb[frf_a4] <= 1'b1;
end end
assign CSRAdrM = testbench.dut.core.priv.priv.csr.CSRAdrM; assign CSRAdrM = testbench.dut.core.priv.priv.csr.CSRAdrM;
@ -333,17 +327,17 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
assign rvvi.intr[0][0] = InterruptW; assign rvvi.intr[0][0] = InterruptW;
assign rvvi.mode[0][0] = PrivilegeModeW; assign rvvi.mode[0][0] = PrivilegeModeW;
assign rvvi.ixl[0][0] = PrivilegeModeW == 2'b11 ? 2'b10 : assign rvvi.ixl[0][0] = PrivilegeModeW == 2'b11 ? 2'b10 :
PrivilegeModeW == 2'b01 ? STATUS_SXL : STATUS_UXL; PrivilegeModeW == 2'b01 ? STATUS_SXL : STATUS_UXL;
assign rvvi.pc_wdata[0][0] = ~FlushW ? PCM : assign rvvi.pc_wdata[0][0] = ~FlushW ? PCM :
~FlushM ? PCE : ~FlushM ? PCE :
~FlushE ? PCD : ~FlushE ? PCD :
~FlushD ? PCF : PCNextF; ~FlushD ? PCF : PCNextF;
for(index = 0; index < `NUM_REGS; index += 1) begin for(index = 0; index < `NUM_REGS; index += 1) begin
assign rvvi.x_wdata[0][0][index] = rf[index]; assign rvvi.x_wdata[0][0][index] = rf[index];
assign rvvi.x_wb[0][0][index] = rf_wb[index]; assign rvvi.x_wb[0][0][index] = rf_wb[index];
assign rvvi.f_wdata[0][0][index] = frf[index]; assign rvvi.f_wdata[0][0][index] = frf[index];
assign rvvi.f_wb[0][0][index] = frf_wb[index]; assign rvvi.f_wb[0][0][index] = frf_wb[index];
end end
// record previous csr value. // record previous csr value.
@ -389,6 +383,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
CSRArrayOld[12'h001] = CSRArray[12'h001]; CSRArrayOld[12'h001] = CSRArray[12'h001];
CSRArrayOld[12'h002] = CSRArray[12'h002]; CSRArrayOld[12'h002] = CSRArray[12'h002];
CSRArrayOld[12'h003] = CSRArray[12'h003]; CSRArrayOld[12'h003] = CSRArray[12'h003];
if (P.XLEN == 32) begin if (P.XLEN == 32) begin
CSRArrayOld[12'h310] = CSRArray[12'h310]; CSRArrayOld[12'h310] = CSRArray[12'h310];
CSRArrayOld[12'h31A] = CSRArray[12'h31A]; CSRArrayOld[12'h31A] = CSRArray[12'h31A];
@ -442,6 +437,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
assign CSR_W[12'h001] = (CSRArrayOld[12'h001] != CSRArray[12'h001]) ? 1 : 0; assign CSR_W[12'h001] = (CSRArrayOld[12'h001] != CSRArray[12'h001]) ? 1 : 0;
assign CSR_W[12'h002] = (CSRArrayOld[12'h002] != CSRArray[12'h002]) ? 1 : 0; assign CSR_W[12'h002] = (CSRArrayOld[12'h002] != CSRArray[12'h002]) ? 1 : 0;
assign CSR_W[12'h003] = (CSRArrayOld[12'h003] != CSRArray[12'h003]) ? 1 : 0; assign CSR_W[12'h003] = (CSRArrayOld[12'h003] != CSRArray[12'h003]) ? 1 : 0;
if (P.XLEN == 32) begin if (P.XLEN == 32) begin
assign CSR_W[12'h310] = (CSRArrayOld[12'h310] != CSRArray[12'h310]) ? 1 : 0; assign CSR_W[12'h310] = (CSRArrayOld[12'h310] != CSRArray[12'h310]) ? 1 : 0;
assign CSR_W[12'h31A] = (CSRArrayOld[12'h31A] != CSRArray[12'h31A]) ? 1 : 0; assign CSR_W[12'h31A] = (CSRArrayOld[12'h31A] != CSRArray[12'h31A]) ? 1 : 0;
@ -485,6 +481,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
assign rvvi.csr_wb[0][0][12'h001] = CSR_W[12'h001]; assign rvvi.csr_wb[0][0][12'h001] = CSR_W[12'h001];
assign rvvi.csr_wb[0][0][12'h002] = CSR_W[12'h002]; assign rvvi.csr_wb[0][0][12'h002] = CSR_W[12'h002];
assign rvvi.csr_wb[0][0][12'h003] = CSR_W[12'h003]; assign rvvi.csr_wb[0][0][12'h003] = CSR_W[12'h003];
if (P.XLEN == 32) begin if (P.XLEN == 32) begin
assign rvvi.csr_wb[0][0][12'h310] = CSR_W[12'h310]; assign rvvi.csr_wb[0][0][12'h310] = CSR_W[12'h310];
assign rvvi.csr_wb[0][0][12'h31A] = CSR_W[12'h31A]; assign rvvi.csr_wb[0][0][12'h31A] = CSR_W[12'h31A];
@ -528,6 +525,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
assign rvvi.csr[0][0][12'h001] = CSRArray[12'h001]; assign rvvi.csr[0][0][12'h001] = CSRArray[12'h001];
assign rvvi.csr[0][0][12'h002] = CSRArray[12'h002]; assign rvvi.csr[0][0][12'h002] = CSRArray[12'h002];
assign rvvi.csr[0][0][12'h003] = CSRArray[12'h003]; assign rvvi.csr[0][0][12'h003] = CSRArray[12'h003];
if (P.XLEN == 32) begin if (P.XLEN == 32) begin
assign rvvi.csr[0][0][12'h310] = CSRArray[12'h310]; assign rvvi.csr[0][0][12'h310] = CSRArray[12'h310];
assign rvvi.csr[0][0][12'h31A] = CSRArray[12'h31A]; assign rvvi.csr[0][0][12'h31A] = CSRArray[12'h31A];
@ -565,49 +563,49 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
end end
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if(rvvi.valid[0][0]) begin if(rvvi.valid[0][0]) begin
if(`STD_LOG) begin if(`STD_LOG) begin
$fwrite(file, "%016x, %08x, %s\t\t", rvvi.pc_rdata[0][0], rvvi.insn[0][0], instrWName); $fwrite(file, "%016x, %08x, %s\t\t", rvvi.pc_rdata[0][0], rvvi.insn[0][0], instrWName);
for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
if(rvvi.x_wb[0][0][index2]) begin if(rvvi.x_wb[0][0][index2]) begin
$fwrite(file, "rf[%02d] = %016x ", index2, rvvi.x_wdata[0][0][index2]); $fwrite(file, "rf[%02d] = %016x ", index2, rvvi.x_wdata[0][0][index2]);
end
end end
for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
if(rvvi.f_wb[0][0][index2]) begin
$fwrite(file, "frf[%02d] = %016x ", index2, rvvi.f_wdata[0][0][index2]);
end
end
for(index2 = 0; index2 < `NUM_CSRS; index2 += 1) begin
if(rvvi.csr_wb[0][0][index2]) begin
$fwrite(file, "csr[%03x] = %016x ", index2, rvvi.csr[0][0][index2]);
end
end
$fwrite(file, "\n");
end end
if(`PRINT_PC_INSTR & !(`PRINT_ALL | `PRINT_MOST)) for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
$display("order = %08d, PC = %08x, insn = %08x", rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0]); if(rvvi.f_wb[0][0][index2]) begin
else if(`PRINT_MOST & !`PRINT_ALL) $fwrite(file, "frf[%02d] = %016x ", index2, rvvi.f_wdata[0][0][index2]);
$display("order = %08d, PC = %010x, insn = %08x, trap = %1d, halt = %1d, intr = %1d, mode = %1x, ixl = %1x, pc_wdata = %010x, x%02d = %016x, f%02d = %016x, csr%03x = %016x", end
rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0], rvvi.trap[0][0], rvvi.halt[0][0], rvvi.intr[0][0], rvvi.mode[0][0], rvvi.ixl[0][0], rvvi.pc_wdata[0][0], rf_a3, rvvi.x_wdata[0][0][rf_a3], frf_a4, rvvi.f_wdata[0][0][frf_a4], CSRAdrW, rvvi.csr[0][0][CSRAdrW]); end
else if(`PRINT_ALL) begin for(index2 = 0; index2 < `NUM_CSRS; index2 += 1) begin
$display("order = %08d, PC = %08x, insn = %08x, trap = %1d, halt = %1d, intr = %1d, mode = %1x, ixl = %1x, pc_wdata = %08x", if(rvvi.csr_wb[0][0][index2]) begin
rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0], rvvi.trap[0][0], rvvi.halt[0][0], rvvi.intr[0][0], rvvi.mode[0][0], rvvi.ixl[0][0], rvvi.pc_wdata[0][0]); $fwrite(file, "csr[%03x] = %016x ", index2, rvvi.csr[0][0][index2]);
for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin end
$display("x%02d = %08x", index2, rvvi.x_wdata[0][0][index2]); end
end $fwrite(file, "\n");
for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin end
$display("f%02d = %08x", index2, rvvi.f_wdata[0][0][index2]); if(`PRINT_PC_INSTR & !(`PRINT_ALL | `PRINT_MOST))
end $display("order = %08d, PC = %08x, insn = %08x", rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0]);
end else if(`PRINT_MOST & !`PRINT_ALL)
if (`PRINT_CSRS) begin $display("order = %08d, PC = %010x, insn = %08x, trap = %1d, halt = %1d, intr = %1d, mode = %1x, ixl = %1x, pc_wdata = %010x, x%02d = %016x, f%02d = %016x, csr%03x = %016x",
for(index2 = 0; index2 < `NUM_CSRS; index2 += 1) begin rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0], rvvi.trap[0][0], rvvi.halt[0][0], rvvi.intr[0][0], rvvi.mode[0][0], rvvi.ixl[0][0], rvvi.pc_wdata[0][0], rf_a3, rvvi.x_wdata[0][0][rf_a3], frf_a4, rvvi.f_wdata[0][0][frf_a4], CSRAdrW, rvvi.csr[0][0][CSRAdrW]);
if(CSR_W[index2]) begin else if(`PRINT_ALL) begin
$display("%t: CSR %03x = %x", $time(), index2, CSRArray[index2]); $display("order = %08d, PC = %08x, insn = %08x, trap = %1d, halt = %1d, intr = %1d, mode = %1x, ixl = %1x, pc_wdata = %08x",
end rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0], rvvi.trap[0][0], rvvi.halt[0][0], rvvi.intr[0][0], rvvi.mode[0][0], rvvi.ixl[0][0], rvvi.pc_wdata[0][0]);
end for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
end $display("x%02d = %08x", index2, rvvi.x_wdata[0][0][index2]);
end end
for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
$display("f%02d = %08x", index2, rvvi.f_wdata[0][0][index2]);
end
end
if (`PRINT_CSRS) begin
for(index2 = 0; index2 < `NUM_CSRS; index2 += 1) begin
if(CSR_W[index2]) begin
$display("%t: CSR %03x = %x", $time(), index2, CSRArray[index2]);
end
end
end
end
if(HaltW) $finish; if(HaltW) $finish;
end end