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Update formatting in an attempt to understand what's happening in this file

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Jordan Carlin 2024-11-13 18:26:53 -08:00
parent 017b3e9872
commit d666a0dd7b
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1 changed files with 193 additions and 195 deletions
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14
testbench/common/wallyTracer.sv
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@ -65,7 +65,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
logic InterruptM, InterruptW; logic InterruptM, InterruptW;
//For VM Verification //For VM Verification
logic [(P.XLEN-1):0] VAdrIM,VAdrDM,VAdrIW,VAdrDW; logic [(P.XLEN-1):0] VAdrIM,VAdrDM,VAdrIW,VAdrDW;
logic [(P.XLEN-1):0] PTE_iM,PTE_dM,PTE_iW,PTE_dW; logic [(P.XLEN-1):0] PTE_iM,PTE_dM,PTE_iW,PTE_dW;
logic [(P.PA_BITS-1):0] PAIM,PADM,PAIW,PADW; logic [(P.PA_BITS-1):0] PAIM,PADM,PAIW,PADW;
@ -73,7 +72,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
logic ReadAccessM,WriteAccessM,ReadAccessW,WriteAccessW; logic ReadAccessM,WriteAccessM,ReadAccessW,WriteAccessW;
logic ExecuteAccessF,ExecuteAccessD,ExecuteAccessE,ExecuteAccessM,ExecuteAccessW; logic ExecuteAccessF,ExecuteAccessD,ExecuteAccessE,ExecuteAccessM,ExecuteAccessW;
assign clk = testbench.dut.clk; assign clk = testbench.dut.clk;
// assign InstrValidF = testbench.dut.core.ieu.InstrValidF; // not needed yet // assign InstrValidF = testbench.dut.core.ieu.InstrValidF; // not needed yet
assign InstrValidD = testbench.dut.core.ieu.c.InstrValidD; assign InstrValidD = testbench.dut.core.ieu.c.InstrValidD;
@ -103,7 +101,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
assign wfiM = testbench.dut.core.priv.priv.wfiM; assign wfiM = testbench.dut.core.priv.priv.wfiM;
assign InterruptM = testbench.dut.core.priv.priv.InterruptM; assign InterruptM = testbench.dut.core.priv.priv.InterruptM;
//FOr VM Verification //For VM Verification
assign VAdrIM = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr; assign VAdrIM = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr;
assign VAdrDM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.VAdr; assign VAdrDM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.VAdr;
assign PAIM = testbench.dut.core.ifu.immu.immu.PhysicalAddress; assign PAIM = testbench.dut.core.ifu.immu.immu.PhysicalAddress;
@ -116,8 +114,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
assign PPN_iM = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN; assign PPN_iM = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN;
assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN;
logic valid; logic valid;
int csrid; int csrid;
@ -127,8 +123,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
// stalled. If it is stalled we want CSRArray to hold the old value. // stalled. If it is stalled we want CSRArray to hold the old value.
if(valid) begin if(valid) begin
// machine CSRs // machine CSRs
// *** missing PMP and performance counters.
// PMPCFG space is 0-15 3a0 - 3af // PMPCFG space is 0-15 3a0 - 3af
int i, i4, i8, csrid; int i, i4, i8, csrid;
logic [P.XLEN-1:0] pmp; logic [P.XLEN-1:0] pmp;
@ -204,7 +198,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
CSRArray[12'h15D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[63:32]; CSRArray[12'h15D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[63:32];
end end
end else begin // hold the old value if the pipeline is stalled. end else begin // hold the old value if the pipeline is stalled.
// PMP CFG 3A0 to 3AF // PMP CFG 3A0 to 3AF
for(csrid='h3A0; csrid<='h3AF; csrid++) for(csrid='h3A0; csrid<='h3AF; csrid++)
CSRArray[csrid] = CSRArrayOld[csrid]; CSRArray[csrid] = CSRArrayOld[csrid];
@ -253,6 +246,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
CSRArray[12'h001] = CSRArrayOld[12'h001]; CSRArray[12'h001] = CSRArrayOld[12'h001];
CSRArray[12'h002] = CSRArrayOld[12'h002]; CSRArray[12'h002] = CSRArrayOld[12'h002];
CSRArray[12'h003] = CSRArrayOld[12'h003]; CSRArray[12'h003] = CSRArrayOld[12'h003];
if (P.XLEN == 32) begin if (P.XLEN == 32) begin
CSRArray[12'h310] = CSRArrayOld[12'h310]; CSRArray[12'h310] = CSRArrayOld[12'h310];
CSRArray[12'h31A] = CSRArrayOld[12'h31A]; CSRArray[12'h31A] = CSRArrayOld[12'h31A];
@ -389,6 +383,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
CSRArrayOld[12'h001] = CSRArray[12'h001]; CSRArrayOld[12'h001] = CSRArray[12'h001];
CSRArrayOld[12'h002] = CSRArray[12'h002]; CSRArrayOld[12'h002] = CSRArray[12'h002];
CSRArrayOld[12'h003] = CSRArray[12'h003]; CSRArrayOld[12'h003] = CSRArray[12'h003];
if (P.XLEN == 32) begin if (P.XLEN == 32) begin
CSRArrayOld[12'h310] = CSRArray[12'h310]; CSRArrayOld[12'h310] = CSRArray[12'h310];
CSRArrayOld[12'h31A] = CSRArray[12'h31A]; CSRArrayOld[12'h31A] = CSRArray[12'h31A];
@ -442,6 +437,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
assign CSR_W[12'h001] = (CSRArrayOld[12'h001] != CSRArray[12'h001]) ? 1 : 0; assign CSR_W[12'h001] = (CSRArrayOld[12'h001] != CSRArray[12'h001]) ? 1 : 0;
assign CSR_W[12'h002] = (CSRArrayOld[12'h002] != CSRArray[12'h002]) ? 1 : 0; assign CSR_W[12'h002] = (CSRArrayOld[12'h002] != CSRArray[12'h002]) ? 1 : 0;
assign CSR_W[12'h003] = (CSRArrayOld[12'h003] != CSRArray[12'h003]) ? 1 : 0; assign CSR_W[12'h003] = (CSRArrayOld[12'h003] != CSRArray[12'h003]) ? 1 : 0;
if (P.XLEN == 32) begin if (P.XLEN == 32) begin
assign CSR_W[12'h310] = (CSRArrayOld[12'h310] != CSRArray[12'h310]) ? 1 : 0; assign CSR_W[12'h310] = (CSRArrayOld[12'h310] != CSRArray[12'h310]) ? 1 : 0;
assign CSR_W[12'h31A] = (CSRArrayOld[12'h31A] != CSRArray[12'h31A]) ? 1 : 0; assign CSR_W[12'h31A] = (CSRArrayOld[12'h31A] != CSRArray[12'h31A]) ? 1 : 0;
@ -485,6 +481,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
assign rvvi.csr_wb[0][0][12'h001] = CSR_W[12'h001]; assign rvvi.csr_wb[0][0][12'h001] = CSR_W[12'h001];
assign rvvi.csr_wb[0][0][12'h002] = CSR_W[12'h002]; assign rvvi.csr_wb[0][0][12'h002] = CSR_W[12'h002];
assign rvvi.csr_wb[0][0][12'h003] = CSR_W[12'h003]; assign rvvi.csr_wb[0][0][12'h003] = CSR_W[12'h003];
if (P.XLEN == 32) begin if (P.XLEN == 32) begin
assign rvvi.csr_wb[0][0][12'h310] = CSR_W[12'h310]; assign rvvi.csr_wb[0][0][12'h310] = CSR_W[12'h310];
assign rvvi.csr_wb[0][0][12'h31A] = CSR_W[12'h31A]; assign rvvi.csr_wb[0][0][12'h31A] = CSR_W[12'h31A];
@ -528,6 +525,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
assign rvvi.csr[0][0][12'h001] = CSRArray[12'h001]; assign rvvi.csr[0][0][12'h001] = CSRArray[12'h001];
assign rvvi.csr[0][0][12'h002] = CSRArray[12'h002]; assign rvvi.csr[0][0][12'h002] = CSRArray[12'h002];
assign rvvi.csr[0][0][12'h003] = CSRArray[12'h003]; assign rvvi.csr[0][0][12'h003] = CSRArray[12'h003];
if (P.XLEN == 32) begin if (P.XLEN == 32) begin
assign rvvi.csr[0][0][12'h310] = CSRArray[12'h310]; assign rvvi.csr[0][0][12'h310] = CSRArray[12'h310];
assign rvvi.csr[0][0][12'h31A] = CSRArray[12'h31A]; assign rvvi.csr[0][0][12'h31A] = CSRArray[12'h31A];