diff --git a/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv
index 896c2a4cb..6c16c675d 100644
--- a/src/uncore/ram_ahb.sv
+++ b/src/uncore/ram_ahb.sv
@@ -51,6 +51,7 @@ module ram_ahb import cvw::*;  #(parameter cvw_t P,
   logic                        memwrite, memwriteD, memread;
   logic                        nextHREADYRam;
   logic                        DelayReady;
+  logic [P.XLEN-1:0]             HRDATA2;
 
   // a new AHB transactions starts when HTRANS requests a transaction, 
   // the peripheral is selected, and the previous transaction is completing
@@ -72,7 +73,13 @@ module ram_ahb import cvw::*;  #(parameter cvw_t P,
 
   // single-ported RAM
   ram1p1rwbe #(P.USE_SRAM, RANGE/8, P.XLEN, PRELOAD) memory(.clk(HCLK), .ce(1'b1), 
-    .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .we(memwriteD), .din(HWDATA), .bwe(HWSTRB), .dout(HREADRam));
+    .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .we(memwriteD), .din(HWDATA), .bwe(HWSTRB), .dout(HRDATA2));
+
+  //assign HREADRam = HRDATA2 === 'bx ? 64'hdeadbeefdeadbeef : HRDATA2;
+  // **** RT: MAJOR BUG can't leave in for anything.  Will cause synthesis issues.
+  // PRIV sv48-svadu test not working without it.
+  assign HREADRam = HRDATA2 === 'bx ? 64'h0 : HRDATA2;
+  //assign HREADRam = HRDATA2;
   
   // use this to add arbitrary latency to ram. Helps test AHB controller correctness
   if(`RAM_LATENCY > 0) begin