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Modified the fpga build script to generate it's own config file rather than use the one in config/fpga.

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This commit is contained in:
Rose Thompson 2023-11-13 17:48:28 -06:00
parent 95fc5f4a1c
commit d5f0c15b90
2 changed files with 20 additions and 1 deletions
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19
fpga/generator/Makefile
View File

@ -50,7 +50,26 @@ IP_Arty: $(dst)/xlnx_proc_sys_reset.log \
PreProcessFiles: PreProcessFiles:
rm -rf ../src/CopiedFiles_do_not_add_to_repo/ rm -rf ../src/CopiedFiles_do_not_add_to_repo/
cp -r ../../src/ ../src/CopiedFiles_do_not_add_to_repo/ cp -r ../../src/ ../src/CopiedFiles_do_not_add_to_repo/
mkdir ../src/CopiedFiles_do_not_add_to_repo/config/
cp ../../config/fpga/config.vh ../src/CopiedFiles_do_not_add_to_repo/config/
./insert_debug_comment.sh ./insert_debug_comment.sh
# modify config *** RT: eventually setup for variably defined sized memory
sed -i "s/ZICCLSM_SUPPORTED.*/ZICCLSM_SUPPORTED = 0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/RESET_VECTOR.*/RESET_VECTOR = 64'h0000000000001000;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/BOOTROM_PRELOAD.*/BOOTROM_PRELOAD = 1'b1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/UNCORE_RAM_BASE.*/UNCORE_RAM_BASE = 64'h00002000;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE = 64'h00000FFF;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/UNCORE_RAM_PRELOAD.*/UNCORE_RAM_PRELOAD = 1'b1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/EXT_MEM_SUPPORTED.*/EXT_MEM_SUPPORTED = 1'b1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/EXT_MEM_RANGE.*/EXT_MEM_RANGE = 64'h0FFFFFFF;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/SDC_SUPPORTED.*/SDC_SUPPORTED = 1'b1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/SPI_SUPPORTED.*/SDC_SUPPORTED = 1'b0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh # *** RT: Add SPI when ready
sed -i "s/GPIO_LOOPBACK_TEST.*/GPIO_LOOPBACK_TEST = 0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/SPI_LOOPBACK_TEST.*/SPI_LOOPBACK_TEST = 0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/UART_PRESCALE.*/UART_PRESCALE = 32'd0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/PLIC_NUM_SRC.*/PLIC_NUM_SRC = 32'd53;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/PLIC_SDC_ID.*/PLIC_SDC_ID = 32'd20;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/BPRED_SIZE.*/BPRED_SIZE = 32'd12;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
$(dst)/%.log: %.tcl $(dst)/%.log: %.tcl
mkdir -p IP mkdir -p IP

2
fpga/generator/wally.tcl
View File

@ -48,7 +48,7 @@ read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_cmd_serial_host.v]
read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_data_master.v] read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_data_master.v]
read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_data_serial_host.v] read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_data_serial_host.v]
set_property include_dirs {../../config/fpga ../../config/shared ../../addins/vivado-risc-v/sdc} [current_fileset] set_property include_dirs {../src/CopiedFiles_do_no_add_to_repo/config/ ../../config/shared ../../addins/vivado-risc-v/sdc} [current_fileset]
if {$board=="ArtyA7"} { if {$board=="ArtyA7"} {
add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc