From d5e8ecbed5dd36c6b02f11a8659fe67e31129e85 Mon Sep 17 00:00:00 2001
From: Rose Thompson <rose@rosethompson.net>
Date: Tue, 12 Nov 2024 15:29:05 -0600
Subject: [PATCH] Simplified the fpgatop SDCCLK logic.

---
 fpga/src/fpgaTop.sv | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/fpga/src/fpgaTop.sv b/fpga/src/fpgaTop.sv
index 7b503e1f1..a1f4849ca 100644
--- a/fpga/src/fpgaTop.sv
+++ b/fpga/src/fpgaTop.sv
@@ -182,7 +182,6 @@ module fpgaTop
   logic [511 : 0]  dbg_bus;
 
   logic		   CLK208;
-  logic		   SDCCLKInternal;
 
   assign GPIOIN = {25'b0, SDCCD, SDCWP, 2'b0, GPI};
   assign GPO = GPIOOUT[4:0];
@@ -216,7 +215,7 @@ module fpgaTop
                     .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
                     .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), 
                     .GPIOIN, .GPIOOUT, .GPIOEN,
-                    .UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS(SDCCSin), .SDCCLK(SDCCLK), .ExternalStall(RVVIStall));
+                    .UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS(SDCCSin), .SDCCLK, .ExternalStall(RVVIStall));
 
 
   // ahb lite to axi bridge