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Merge pull request #322 from harshinisrinath1001/main

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Fixing spacing for ebu
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David Harris 2023-06-11 06:00:35 -07:00 committed by GitHub
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6 changed files with 36 additions and 46 deletions
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22
src/ebu/ahbcacheinterface.sv
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@ -45,14 +45,14 @@ module ahbcacheinterface #(
output logic [2:0] HSIZE, // AHB transaction width output logic [2:0] HSIZE, // AHB transaction width
output logic [2:0] HBURST, // AHB burst length output logic [2:0] HBURST, // AHB burst length
// bus interface buses // bus interface buses
input logic [AHBW-1:0] HRDATA, // AHB read data input logic [AHBW-1:0] HRDATA, // AHB read data
output logic [PA_BITS-1:0] HADDR, // AHB address output logic [PA_BITS-1:0] HADDR, // AHB address
output logic [AHBW-1:0] HWDATA, // AHB write data output logic [AHBW-1:0] HWDATA, // AHB write data
output logic [AHBW/8-1:0] HWSTRB, // AHB byte mask output logic [AHBW/8-1:0] HWSTRB, // AHB byte mask
// cache interface // cache interface
input logic [PA_BITS-1:0] CacheBusAdr, // Address of cache line input logic [PA_BITS-1:0] CacheBusAdr, // Address of cache line
input logic [LLEN-1:0] CacheReadDataWordM, // One word of cache line during a writeback input logic [LLEN-1:0] CacheReadDataWordM, // One word of cache line during a writeback
input logic CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$ input logic CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$
input logic Cacheable, // Memory operation is cachable input logic Cacheable, // Memory operation is cachable
input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch
@ -62,8 +62,8 @@ module ahbcacheinterface #(
output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr
// uncached interface // uncached interface
input logic [PA_BITS-1:0] PAdr, // Physical address of uncached memory operation input logic [PA_BITS-1:0] PAdr, // Physical address of uncached memory operation
input logic [LLEN-1:0] WriteDataM, // IEU write data for uncached store input logic [LLEN-1:0] WriteDataM, // IEU write data for uncached store
input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write
input logic [2:0] Funct3, // Size of uncached memory operation input logic [2:0] Funct3, // Size of uncached memory operation
@ -75,11 +75,11 @@ module ahbcacheinterface #(
localparam BeatCountThreshold = BEATSPERLINE - 1; // Largest beat index localparam BeatCountThreshold = BEATSPERLINE - 1; // Largest beat index
logic [PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation logic [PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation
logic [AHBWLOGBWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage logic [AHBWLOGBWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage
logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA
logic [AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s logic [AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s
logic [AHBW-1:0] PreHWDATA; // AHB Address phase write data logic [AHBW-1:0] PreHWDATA; // AHB Address phase write data
genvar index; genvar index;

12
src/ebu/ahbinterface.sv
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@ -36,19 +36,19 @@ module ahbinterface #(
input logic HREADY, // AHB peripheral ready input logic HREADY, // AHB peripheral ready
output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
output logic HWRITE, // AHB 0: Read operation 1: Write operation output logic HWRITE, // AHB 0: Read operation 1: Write operation
input logic [XLEN-1:0] HRDATA, // AHB read data input logic [XLEN-1:0] HRDATA, // AHB read data
output logic [XLEN-1:0] HWDATA, // AHB write data output logic [XLEN-1:0] HWDATA, // AHB write data
output logic [XLEN/8-1:0] HWSTRB, // AHB byte mask output logic [XLEN/8-1:0] HWSTRB, // AHB byte mask
// lsu/ifu interface // lsu/ifu interface
input logic Stall, // Core pipeline is stalled input logic Stall, // Core pipeline is stalled
input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting
input logic [1:0] BusRW, // Memory operation read/write control: 10: read, 01: write input logic [1:0] BusRW, // Memory operation read/write control: 10: read, 01: write
input logic [XLEN/8-1:0] ByteMask, // Bytes enables within a word input logic [XLEN/8-1:0] ByteMask, // Bytes enables within a word
input logic [XLEN-1:0] WriteData, // IEU write data for a store input logic [XLEN-1:0] WriteData, // IEU write data for a store
output logic BusStall, // Bus is busy with an in flight memory operation output logic BusStall, // Bus is busy with an in flight memory operation
output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
output logic [(LSU ? XLEN : 32)-1:0] FetchBuffer // Register to hold HRDATA after arriving from the bus output logic [(LSU ? XLEN : 32)-1:0] FetchBuffer // Register to hold HRDATA after arriving from the bus
); );
logic CaptureEn; logic CaptureEn;

9
src/ebu/controllerinput.sv
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@ -46,14 +46,14 @@ module controllerinput #(
input logic HWRITEIn, // Manager input. AHB 0: Read operation 1: Write operation input logic HWRITEIn, // Manager input. AHB 0: Read operation 1: Write operation
input logic [2:0] HSIZEIn, // Manager input. AHB transaction width input logic [2:0] HSIZEIn, // Manager input. AHB transaction width
input logic [2:0] HBURSTIn, // Manager input. AHB burst length input logic [2:0] HBURSTIn, // Manager input. AHB burst length
input logic [PA_BITS-1:0] HADDRIn, // Manager input. AHB address input logic [PA_BITS-1:0] HADDRIn, // Manager input. AHB address
output logic HREADYOut, // Indicate to manager the peripheral is not busy and another manager does not have priority output logic HREADYOut, // Indicate to manager the peripheral is not busy and another manager does not have priority
// controller output // controller output
output logic [1:0] HTRANSOut, // Arbitrated manager transaction. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ output logic [1:0] HTRANSOut, // Arbitrated manager transaction. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
output logic HWRITEOut, // Arbitrated manager transaction. AHB 0: Read operation 1: Write operation output logic HWRITEOut, // Arbitrated manager transaction. AHB 0: Read operation 1: Write operation
output logic [2:0] HSIZEOut, // Arbitrated manager transaction. AHB transaction width output logic [2:0] HSIZEOut, // Arbitrated manager transaction. AHB transaction width
output logic [2:0] HBURSTOut, // Arbitrated manager transaction. AHB burst length output logic [2:0] HBURSTOut, // Arbitrated manager transaction. AHB burst length
output logic [PA_BITS-1:0] HADDROut, // Arbitrated manager transaction. AHB address output logic [PA_BITS-1:0] HADDROut, // Arbitrated manager transaction. AHB address
input logic HREADYIn // Peripheral ready input logic HREADYIn // Peripheral ready
); );
@ -61,7 +61,7 @@ module controllerinput #(
logic [2:0] HSIZESave; logic [2:0] HSIZESave;
logic [2:0] HBURSTSave; logic [2:0] HBURSTSave;
logic [1:0] HTRANSSave; logic [1:0] HTRANSSave;
logic [PA_BITS-1:0] HADDRSave; logic [PA_BITS-1:0] HADDRSave;
if (SAVE_ENABLED) begin if (SAVE_ENABLED) begin
flopenr #(1+3+3+2+PA_BITS) SaveReg(HCLK, ~HRESETn, Save, flopenr #(1+3+3+2+PA_BITS) SaveReg(HCLK, ~HRESETn, Save,
@ -83,6 +83,3 @@ module controllerinput #(
assign HREADYOut = HREADYIn & ~Disable; assign HREADYOut = HREADYIn & ~Disable;
endmodule endmodule

2
src/fpu/fclassify.sv
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@ -33,7 +33,7 @@ module fclassify import cvw::*; #(parameter cvw_t P) (
input logic XSubnorm, // is Subnormal input logic XSubnorm, // is Subnormal
input logic XZero, // is zero input logic XZero, // is zero
input logic XInf, // is infinity input logic XInf, // is infinity
output logic [P.XLEN-1:0] ClassRes // classify result output logic [P.XLEN-1:0] ClassRes // classify result
); );
logic PInf, PZero, PNorm, PSubnorm; // is the input a positive infinity/zero/normal/subnormal logic PInf, PZero, PNorm, PSubnorm; // is the input a positive infinity/zero/normal/subnormal

25
src/fpu/fcmp.sv
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@ -1,4 +1,3 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// fcmp.sv // fcmp.sv
// //
@ -36,23 +35,23 @@
module fcmp import cvw::*; #(parameter cvw_t P) ( module fcmp import cvw::*; #(parameter cvw_t P) (
input logic [P.FMTBITS-1:0] Fmt, // format of fp number input logic [P.FMTBITS-1:0] Fmt, // format of fp number
input logic [2:0] OpCtrl, // see above table input logic [2:0] OpCtrl, // see above table
input logic Xs, Ys, // input signs input logic Xs, Ys, // input signs
input logic [P.NE-1:0] Xe, Ye, // input exponents input logic [P.NE-1:0] Xe, Ye, // input exponents
input logic [P.NF:0] Xm, Ym, // input mantissa input logic [P.NF:0] Xm, Ym, // input mantissa
input logic XZero, YZero, // is zero input logic XZero, YZero, // is zero
input logic XNaN, YNaN, // is NaN input logic XNaN, YNaN, // is NaN
input logic XSNaN, YSNaN, // is signaling NaN input logic XSNaN, YSNaN, // is signaling NaN
input logic [P.FLEN-1:0] X, Y, // original inputs (before unpacker) input logic [P.FLEN-1:0] X, Y, // original inputs (before unpacker)
output logic CmpNV, // invalid flag output logic CmpNV, // invalid flag
output logic [P.FLEN-1:0] CmpFpRes, // compare floating-point result output logic [P.FLEN-1:0] CmpFpRes, // compare floating-point result
output logic [P.XLEN-1:0] CmpIntRes // compare integer result output logic [P.XLEN-1:0] CmpIntRes // compare integer result
); );
logic LTabs, LT, EQ; // is X < or > or = Y logic LTabs, LT, EQ; // is X < or > or = Y
logic [P.FLEN-1:0] NaNRes; // NaN result logic [P.FLEN-1:0] NaNRes; // NaN result
logic BothZero; // are both inputs zero logic BothZero; // are both inputs zero
logic EitherNaN, EitherSNaN; // are either input a (signaling) NaN logic EitherNaN, EitherSNaN; // are either input a (signaling) NaN
assign LTabs= {1'b0, Xe, Xm} < {1'b0, Ye, Ym}; // unsigned comparison, treating FP as integers assign LTabs= {1'b0, Xe, Xm} < {1'b0, Ye, Ym}; // unsigned comparison, treating FP as integers
assign LT = (Xs & ~Ys) | (Xs & Ys & ~LTabs & ~EQ) | (~Xs & ~Ys & LTabs); // signed comparison assign LT = (Xs & ~Ys) | (Xs & Ys & ~LTabs & ~EQ) | (~Xs & ~Ys & LTabs); // signed comparison
@ -62,7 +61,6 @@ module fcmp import cvw::*; #(parameter cvw_t P) (
assign EitherNaN = XNaN|YNaN; assign EitherNaN = XNaN|YNaN;
assign EitherSNaN = XSNaN|YSNaN; assign EitherSNaN = XSNaN|YSNaN;
// flags // flags
// Min/Max - if an input is a signaling NaN set invalid flag // Min/Max - if an input is a signaling NaN set invalid flag
// LT/LE - signaling - sets invalid if NaN input // LT/LE - signaling - sets invalid if NaN input
@ -85,11 +83,11 @@ module fcmp import cvw::*; #(parameter cvw_t P) (
// select the NaN result // select the NaN result
if (P.FPSIZES == 1) if (P.FPSIZES == 1)
if(P.IEEE754) assign NaNRes = {Xs, {P.NE{1'b1}}, 1'b1, Xm[P.NF-2:0]}; if(P.IEEE754) assign NaNRes = {Xs, {P.NE{1'b1}}, 1'b1, Xm[P.NF-2:0]};
else assign NaNRes = {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}}; else assign NaNRes = {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}};
else if (P.FPSIZES == 2) else if (P.FPSIZES == 2)
if(P.IEEE754) assign NaNRes = Fmt ? {Xs, {P.NE{1'b1}}, 1'b1, Xm[P.NF-2:0]} : {{P.FLEN-P.LEN1{1'b1}}, Xs, {P.NE1{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.NF1]}; if(P.IEEE754) assign NaNRes = Fmt ? {Xs, {P.NE{1'b1}}, 1'b1, Xm[P.NF-2:0]} : {{P.FLEN-P.LEN1{1'b1}}, Xs, {P.NE1{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.NF1]};
else assign NaNRes = Fmt ? {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}} : {{P.FLEN-P.LEN1{1'b1}}, 1'b0, {P.NE1{1'b1}}, 1'b1, (P.NF1-1)'(0)}; else assign NaNRes = Fmt ? {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}} : {{P.FLEN-P.LEN1{1'b1}}, 1'b0, {P.NE1{1'b1}}, 1'b1, (P.NF1-1)'(0)};
else if (P.FPSIZES == 3) else if (P.FPSIZES == 3)
always_comb always_comb
@ -123,7 +121,6 @@ module fcmp import cvw::*; #(parameter cvw_t P) (
else NaNRes = {{P.FLEN-P.H_LEN{1'b1}}, 1'b0, {P.H_NE{1'b1}}, 1'b1, (P.H_NF-1)'(0)}; else NaNRes = {{P.FLEN-P.H_LEN{1'b1}}, 1'b0, {P.H_NE{1'b1}}, 1'b1, (P.H_NF-1)'(0)};
endcase endcase
// Min/Max // Min/Max
// - outputs the min/max of X and Y // - outputs the min/max of X and Y
// - -0 < 0 // - -0 < 0

12
src/fpu/fctrl.sv
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@ -48,7 +48,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
// opperation mux selections // opperation mux selections
output logic FCvtIntE, FCvtIntW, // convert to integer opperation output logic FCvtIntE, FCvtIntW, // convert to integer opperation
output logic [2:0] FrmM, // FP rounding mode output logic [2:0] FrmM, // FP rounding mode
output logic [P.FMTBITS-1:0] FmtE, FmtM, // FP format output logic [P.FMTBITS-1:0] FmtE, FmtM, // FP format
output logic [2:0] OpCtrlE, OpCtrlM, // Select which opperation to do in each component output logic [2:0] OpCtrlE, OpCtrlM, // Select which opperation to do in each component
output logic FpLoadStoreM, // FP load or store instruction output logic FpLoadStoreM, // FP load or store instruction
output logic [1:0] PostProcSelE, PostProcSelM, // select result in the post processing unit output logic [1:0] PostProcSelE, PostProcSelM, // select result in the post processing unit
@ -73,7 +73,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
logic [1:0] PostProcSelD; // select result in the post processing unit logic [1:0] PostProcSelD; // select result in the post processing unit
logic [1:0] FResSelD; // Select one of the results that finish in the memory stage logic [1:0] FResSelD; // Select one of the results that finish in the memory stage
logic [2:0] FrmD, FrmE; // FP rounding mode logic [2:0] FrmD, FrmE; // FP rounding mode
logic [P.FMTBITS-1:0] FmtD; // FP format logic [P.FMTBITS-1:0] FmtD; // FP format
logic [1:0] Fmt, Fmt2; // format - before possible reduction logic [1:0] Fmt, Fmt2; // format - before possible reduction
logic SupportedFmt; // is the format supported logic SupportedFmt; // is the format supported
logic SupportedFmt2; // is the source format supported for fp -> fp logic SupportedFmt2; // is the source format supported for fp -> fp
@ -232,8 +232,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
logic [1:0] FmtTmp; logic [1:0] FmtTmp;
assign FmtTmp = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : (~OpD[6]&(&OpD[2:0])) ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : Funct7D[1:0]; assign FmtTmp = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : (~OpD[6]&(&OpD[2:0])) ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : Funct7D[1:0];
assign FmtD = (P.FMT == FmtTmp); assign FmtD = (P.FMT == FmtTmp);
end end else if (P.FPSIZES == 3|P.FPSIZES == 4)
else if (P.FPSIZES == 3|P.FPSIZES == 4)
assign FmtD = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0]; assign FmtD = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0];
// Enables indicate that a source register is used and may need stalls. Also indicate special cases for infinity or NaN. // Enables indicate that a source register is used and may need stalls. Also indicate special cases for infinity or NaN.
@ -250,12 +249,9 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
((FResSelD==2'b11)&(PostProcSelD==2'b00))| // mv float to int ((FResSelD==2'b11)&(PostProcSelD==2'b00))| // mv float to int
((FResSelD==2'b01)&((PostProcSelD==2'b00)|((PostProcSelD==2'b01)&OpCtrlD[0])))); // cvt both or sqrt ((FResSelD==2'b01)&((PostProcSelD==2'b00)|((PostProcSelD==2'b01)&OpCtrlD[0])))); // cvt both or sqrt
// Z - fma ops only // Z - fma ops only
assign ZEnD = (PostProcSelD==2'b10)&(~OpCtrlD[2]|OpCtrlD[1]); // fma, add, sub assign ZEnD = (PostProcSelD==2'b10)&(~OpCtrlD[2]|OpCtrlD[1]); // fma, add, sub
// Final Res Sel: // Final Res Sel:
// fp int // fp int
// 00 other cmp // 00 other cmp
@ -321,7 +317,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
// Integer division on FPU divider // Integer division on FPU divider
if (P.M_SUPPORTED & P.IDIV_ON_FPU) assign IDivStartE = IntDivE; if (P.M_SUPPORTED & P.IDIV_ON_FPU) assign IDivStartE = IntDivE;
else assign IDivStartE = 0; else assign IDivStartE = 0;
// E/M pipleine register // E/M pipleine register
flopenrc #(13+int'(P.FMTBITS)) EMCtrlReg (clk, reset, FlushM, ~StallM, flopenrc #(13+int'(P.FMTBITS)) EMCtrlReg (clk, reset, FlushM, ~StallM,