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https://github.com/openhwgroup/cvw
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Merge pull request #322 from harshinisrinath1001/main
Fixing spacing for ebu
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commit
d5b237e728
@ -83,6 +83,3 @@ module controllerinput #(
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assign HREADYOut = HREADYIn & ~Disable;
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assign HREADYOut = HREADYIn & ~Disable;
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endmodule
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endmodule
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@ -1,4 +1,3 @@
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///////////////////////////////////////////
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///////////////////////////////////////////
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// fcmp.sv
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// fcmp.sv
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//
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//
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@ -62,7 +61,6 @@ module fcmp import cvw::*; #(parameter cvw_t P) (
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assign EitherNaN = XNaN|YNaN;
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assign EitherNaN = XNaN|YNaN;
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assign EitherSNaN = XSNaN|YSNaN;
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assign EitherSNaN = XSNaN|YSNaN;
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// flags
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// flags
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// Min/Max - if an input is a signaling NaN set invalid flag
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// Min/Max - if an input is a signaling NaN set invalid flag
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// LT/LE - signaling - sets invalid if NaN input
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// LT/LE - signaling - sets invalid if NaN input
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@ -123,7 +121,6 @@ module fcmp import cvw::*; #(parameter cvw_t P) (
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else NaNRes = {{P.FLEN-P.H_LEN{1'b1}}, 1'b0, {P.H_NE{1'b1}}, 1'b1, (P.H_NF-1)'(0)};
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else NaNRes = {{P.FLEN-P.H_LEN{1'b1}}, 1'b0, {P.H_NE{1'b1}}, 1'b1, (P.H_NF-1)'(0)};
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endcase
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endcase
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// Min/Max
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// Min/Max
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// - outputs the min/max of X and Y
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// - outputs the min/max of X and Y
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// - -0 < 0
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// - -0 < 0
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@ -232,8 +232,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
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logic [1:0] FmtTmp;
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logic [1:0] FmtTmp;
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assign FmtTmp = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : (~OpD[6]&(&OpD[2:0])) ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : Funct7D[1:0];
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assign FmtTmp = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : (~OpD[6]&(&OpD[2:0])) ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : Funct7D[1:0];
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assign FmtD = (P.FMT == FmtTmp);
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assign FmtD = (P.FMT == FmtTmp);
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end
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end else if (P.FPSIZES == 3|P.FPSIZES == 4)
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else if (P.FPSIZES == 3|P.FPSIZES == 4)
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assign FmtD = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0];
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assign FmtD = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0];
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// Enables indicate that a source register is used and may need stalls. Also indicate special cases for infinity or NaN.
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// Enables indicate that a source register is used and may need stalls. Also indicate special cases for infinity or NaN.
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@ -250,12 +249,9 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
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((FResSelD==2'b11)&(PostProcSelD==2'b00))| // mv float to int
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((FResSelD==2'b11)&(PostProcSelD==2'b00))| // mv float to int
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((FResSelD==2'b01)&((PostProcSelD==2'b00)|((PostProcSelD==2'b01)&OpCtrlD[0])))); // cvt both or sqrt
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((FResSelD==2'b01)&((PostProcSelD==2'b00)|((PostProcSelD==2'b01)&OpCtrlD[0])))); // cvt both or sqrt
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// Z - fma ops only
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// Z - fma ops only
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assign ZEnD = (PostProcSelD==2'b10)&(~OpCtrlD[2]|OpCtrlD[1]); // fma, add, sub
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assign ZEnD = (PostProcSelD==2'b10)&(~OpCtrlD[2]|OpCtrlD[1]); // fma, add, sub
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// Final Res Sel:
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// Final Res Sel:
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// fp int
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// fp int
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// 00 other cmp
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// 00 other cmp
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