mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Replaced muxing of upper address bits with disregarding their match. Moved WriteEnables gate into tlblru to eliminate WriteLines
This commit is contained in:
parent
694badcc6b
commit
d58cad89a8
@ -91,10 +91,10 @@ module tlb #(parameter TLB_ENTRIES = 8,
|
|||||||
logic Translate;
|
logic Translate;
|
||||||
|
|
||||||
// Store current virtual memory mode (SV32, SV39, SV48, ect...)
|
// Store current virtual memory mode (SV32, SV39, SV48, ect...)
|
||||||
logic [`SVMODE_BITS-1:0] SvMode;
|
//logic [`SVMODE_BITS-1:0] SvMode;
|
||||||
logic [1:0] EffectivePrivilegeMode; // privilege mode, possibly modified by MPRV
|
logic [1:0] EffectivePrivilegeMode; // privilege mode, possibly modified by MPRV
|
||||||
|
|
||||||
logic [TLB_ENTRIES-1:0] ReadLines, WriteLines, WriteEnables, PTE_G; // used as the one-hot encoding of WriteIndex
|
logic [TLB_ENTRIES-1:0] ReadLines, WriteEnables, PTE_G; // used as the one-hot encoding of WriteIndex
|
||||||
|
|
||||||
// Sections of the virtual and physical addresses
|
// Sections of the virtual and physical addresses
|
||||||
logic [`VPN_BITS-1:0] VirtualPageNumber;
|
logic [`VPN_BITS-1:0] VirtualPageNumber;
|
||||||
@ -106,29 +106,17 @@ module tlb #(parameter TLB_ENTRIES = 8,
|
|||||||
logic [7:0] PTEAccessBits;
|
logic [7:0] PTEAccessBits;
|
||||||
logic [11:0] PageOffset;
|
logic [11:0] PageOffset;
|
||||||
|
|
||||||
logic PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R; // Useful PTE Control Bits
|
logic PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R; // Useful PTE Control Bits
|
||||||
logic [1:0] HitPageType;
|
logic [1:0] HitPageType;
|
||||||
logic CAMHit;
|
logic CAMHit;
|
||||||
|
logic SV39Mode;
|
||||||
logic [`ASID_BITS-1:0] ASID;
|
logic [`ASID_BITS-1:0] ASID;
|
||||||
|
|
||||||
// Grab the sv mode from SATP and determine whether translation should occur
|
// Grab the sv mode from SATP and determine whether translation should occur
|
||||||
assign ASID = SATP_REGW[`ASID_BASE+`ASID_BITS-1:`ASID_BASE];
|
assign ASID = SATP_REGW[`ASID_BASE+`ASID_BITS-1:`ASID_BASE];
|
||||||
|
|
||||||
// Determine whether to write TLB
|
// Determine whether to write TLB
|
||||||
assign WriteEnables = WriteLines & {(TLB_ENTRIES){TLBWrite}};
|
assign VirtualPageNumber = VirtualAddress[`VPN_BITS+11:12];
|
||||||
|
|
||||||
// The bus width is always the largest it could be for that XLEN. For example, vpn will be 36 bits wide in rv64
|
|
||||||
// this, even though it could be 27 bits (SV39) or 36 bits (SV48) wide. When the value of VPN is narrower,
|
|
||||||
// is shorter, the extra bits are used as padded zeros on the left of the full value.
|
|
||||||
generate
|
|
||||||
if (`XLEN == 32) begin
|
|
||||||
assign VirtualPageNumber = VirtualAddress[`VPN_BITS+11:12];
|
|
||||||
end else begin
|
|
||||||
assign VirtualPageNumber = (SvMode == `SV48) ?
|
|
||||||
VirtualAddress[`VPN_BITS+11:12] :
|
|
||||||
{{`VPN_SEGMENT_BITS{1'b0}}, VirtualAddress[3*`VPN_SEGMENT_BITS+11:12]};
|
|
||||||
end
|
|
||||||
endgenerate
|
|
||||||
|
|
||||||
tlbcontrol tlbcontrol(.*);
|
tlbcontrol tlbcontrol(.*);
|
||||||
|
|
||||||
|
@ -34,6 +34,7 @@ module tlbcam #(parameter TLB_ENTRIES = 8,
|
|||||||
input logic clk, reset,
|
input logic clk, reset,
|
||||||
input logic [`VPN_BITS-1:0] VirtualPageNumber,
|
input logic [`VPN_BITS-1:0] VirtualPageNumber,
|
||||||
input logic [1:0] PageTypeWriteVal,
|
input logic [1:0] PageTypeWriteVal,
|
||||||
|
input logic SV39Mode,
|
||||||
input logic TLBFlush,
|
input logic TLBFlush,
|
||||||
input logic [TLB_ENTRIES-1:0] WriteEnables,
|
input logic [TLB_ENTRIES-1:0] WriteEnables,
|
||||||
input logic [TLB_ENTRIES-1:0] PTE_G,
|
input logic [TLB_ENTRIES-1:0] PTE_G,
|
||||||
|
@ -33,6 +33,7 @@ module tlbcamline #(parameter KEY_BITS = 20,
|
|||||||
input logic clk, reset,
|
input logic clk, reset,
|
||||||
input logic [`VPN_BITS-1:0] VirtualPageNumber, // The requested page number to compare against the key
|
input logic [`VPN_BITS-1:0] VirtualPageNumber, // The requested page number to compare against the key
|
||||||
input logic [`ASID_BITS-1:0] ASID,
|
input logic [`ASID_BITS-1:0] ASID,
|
||||||
|
input logic SV39Mode,
|
||||||
input logic WriteEnable, // Write a new entry to this line
|
input logic WriteEnable, // Write a new entry to this line
|
||||||
input logic PTE_G,
|
input logic PTE_G,
|
||||||
input logic [1:0] PageTypeWriteVal,
|
input logic [1:0] PageTypeWriteVal,
|
||||||
@ -86,7 +87,7 @@ module tlbcamline #(parameter KEY_BITS = 20,
|
|||||||
assign Match0 = (Query0 == Key0) || (PageType > 2'd0); // least signifcant section
|
assign Match0 = (Query0 == Key0) || (PageType > 2'd0); // least signifcant section
|
||||||
assign Match1 = (Query1 == Key1) || (PageType > 2'd1);
|
assign Match1 = (Query1 == Key1) || (PageType > 2'd1);
|
||||||
assign Match2 = (Query2 == Key2) || (PageType > 2'd2);
|
assign Match2 = (Query2 == Key2) || (PageType > 2'd2);
|
||||||
assign Match3 = (Query3 == Key3); // this should always match in sv39 since both vPN3 and key3 are zeroed by the pagetable walker before getting to the cam
|
assign Match3 = (Query3 == Key3) || SV39Mode; // this should always match in sv39 because they aren't used
|
||||||
|
|
||||||
assign Match = Match0 & Match1 & Match2 & Match3 & Valid;
|
assign Match = Match0 & Match1 & Match2 & Match3 & Valid;
|
||||||
end
|
end
|
||||||
|
@ -49,21 +49,26 @@ module tlbcontrol #(parameter TLB_ENTRIES = 8,
|
|||||||
output logic TLBHit,
|
output logic TLBHit,
|
||||||
output logic TLBPageFault,
|
output logic TLBPageFault,
|
||||||
output logic [1:0] EffectivePrivilegeMode,
|
output logic [1:0] EffectivePrivilegeMode,
|
||||||
output logic [`SVMODE_BITS-1:0] SvMode,
|
output logic SV39Mode,
|
||||||
output logic Translate
|
output logic Translate
|
||||||
);
|
);
|
||||||
|
|
||||||
// Sections of the page table entry
|
// Sections of the page table entry
|
||||||
logic [11:0] PageOffset;
|
logic [11:0] PageOffset;
|
||||||
|
logic [`SVMODE_BITS-1:0] SVMode;
|
||||||
|
|
||||||
logic PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R; // Useful PTE Control Bits
|
logic PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R; // Useful PTE Control Bits
|
||||||
logic DAFault;
|
logic DAFault;
|
||||||
logic TLBAccess;
|
logic TLBAccess;
|
||||||
|
|
||||||
// Grab the sv mode from SATP and determine whether translation should occur
|
// Grab the sv mode from SATP and determine whether translation should occur
|
||||||
assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
|
assign SVMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
|
||||||
assign EffectivePrivilegeMode = (ITLB == 1) ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW); // DTLB uses MPP mode when MPRV is 1
|
assign EffectivePrivilegeMode = (ITLB == 1) ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW); // DTLB uses MPP mode when MPRV is 1
|
||||||
assign Translate = (SvMode != `NO_TRANSLATE) & (EffectivePrivilegeMode != `M_MODE) & ~ DisableTranslation;
|
assign Translate = (SVMode != `NO_TRANSLATE) & (EffectivePrivilegeMode != `M_MODE) & ~ DisableTranslation;
|
||||||
|
generate
|
||||||
|
if (`XLEN==64) assign SV39Mode = (SVMode == `SV39);
|
||||||
|
else assign SV39Mode = 0;
|
||||||
|
endgenerate
|
||||||
|
|
||||||
// Determine whether TLB is being used
|
// Determine whether TLB is being used
|
||||||
assign TLBAccess = ReadAccess || WriteAccess;
|
assign TLBAccess = ReadAccess || WriteAccess;
|
||||||
|
@ -30,10 +30,11 @@ module tlblru #(parameter TLB_ENTRIES = 8) (
|
|||||||
input logic TLBFlush,
|
input logic TLBFlush,
|
||||||
input logic [TLB_ENTRIES-1:0] ReadLines,
|
input logic [TLB_ENTRIES-1:0] ReadLines,
|
||||||
input logic CAMHit,
|
input logic CAMHit,
|
||||||
output logic [TLB_ENTRIES-1:0] WriteLines
|
output logic [TLB_ENTRIES-1:0] WriteEnables
|
||||||
);
|
);
|
||||||
|
|
||||||
logic [TLB_ENTRIES-1:0] RUBits, RUBitsNext, RUBitsAccessed;
|
logic [TLB_ENTRIES-1:0] RUBits, RUBitsNext, RUBitsAccessed;
|
||||||
|
logic [TLB_ENTRIES-1:0] WriteLines;
|
||||||
logic [TLB_ENTRIES-1:0] AccessLines; // One-hot encodings of which line is being accessed
|
logic [TLB_ENTRIES-1:0] AccessLines; // One-hot encodings of which line is being accessed
|
||||||
logic AllUsed; // High if the next access causes all RU bits to be 1
|
logic AllUsed; // High if the next access causes all RU bits to be 1
|
||||||
|
|
||||||
@ -41,6 +42,7 @@ module tlblru #(parameter TLB_ENTRIES = 8) (
|
|||||||
tlbpriority #(TLB_ENTRIES) nru(~RUBits, WriteLines);
|
tlbpriority #(TLB_ENTRIES) nru(~RUBits, WriteLines);
|
||||||
|
|
||||||
// Track recently used lines, updating on a CAM Hit or TLB write
|
// Track recently used lines, updating on a CAM Hit or TLB write
|
||||||
|
assign WriteEnables = WriteLines & {(TLB_ENTRIES){TLBWrite}};
|
||||||
assign AccessLines = TLBWrite ? WriteLines : ReadLines;
|
assign AccessLines = TLBWrite ? WriteLines : ReadLines;
|
||||||
assign RUBitsAccessed = AccessLines | RUBits;
|
assign RUBitsAccessed = AccessLines | RUBits;
|
||||||
assign AllUsed = &RUBitsAccessed; // if all recently used, then clear to none
|
assign AllUsed = &RUBitsAccessed; // if all recently used, then clear to none
|
||||||
|
Loading…
Reference in New Issue
Block a user