Merge branch 'main' of github.com:ross144/cvw

addins/embench-iot

@@ -1 +1 @@
-Subproject commit 4c5eb87983f51ca7fcf7855306877b3d1c3aabf1
+Subproject commit 54fd9a0f10aabc662991567ca19ff3e61bfd3939

benchmarks/embench/embench_arch_sweep.py

@@ -10,8 +10,7 @@ from datetime import datetime
 import re
 import collections
 
-#archs = ["rv32i_zicsr", "rv32im_zicsr", "rv32imc_zicsr", "rv32imc_zba_zbb_zbc_zbs_zicsr", "rv32imafdc_zba_zbb_zbc_zbs_zicsr"]
+archs = ["rv32i_zicsr", "rv32im_zicsr", "rv32imc_zicsr", "rv32imc_zba_zbb_zbc_zbs_zicsr", "rv32imafdc_zba_zbb_zbc_zbs_zicsr"]
-archs = ["rv32imafdc_zba_zbb_zbc_zbs_zicsr", "rv32i_zicsr", "rv32im_zicsr", "rv32imc_zicsr", "rv32imc_zba_zbb_zbc_zbs_zicsr"]
 
 def calcgeomean(d, arch):
     progs = ["aha-mont64", "crc32", "cubic", "edn", "huffbench", "matmult-int", "minver", "nbody", "nettle-aes", "nettle-sha256", "nsichneu", "picojpeg", "qrduino", "sglib-combined", "slre", "st", "statemate", "ud", "wikisort"]
@@ -24,7 +23,8 @@ def calcgeomean(d, arch):
     return result
 
 def tabulate_arch_sweep(directory):
-    for case in ["wallySizeOpt_size", "wallySpeedOpt_speed"]:
+    for case in ["wallySizeOpt_size", "wallySpeedOpt_size",  "wallySizeOpt_speed", "wallySpeedOpt_speed"]:
+        print(case)
         d = collections.defaultdict(dict)
         for arch in archs:
             file = case+"_"+arch+".json"
@@ -60,7 +60,7 @@ def tabulate_arch_sweep(directory):
         for arch in archs:
             geomean = calcgeomean(d, arch)
             print(geomean, end="\t")
-        print("")
+        print("\n\n")
  
 def run_arch_sweep():
     # make a folder whose name depends on the date
@@ -83,5 +83,5 @@ def run_arch_sweep():
     return dir
 
 directory = run_arch_sweep()
-#directory = "run_20231117_082325"
+#directory = "run_20231120_072037-caches"
 tabulate_arch_sweep(directory)

config/buildroot/config.vh

@@ -100,7 +100,7 @@ localparam logic [63:0] BOOTROM_RANGE =  64'h00000FFF;
 localparam BOOTROM_PRELOAD = 1'b1;
 localparam UNCORE_RAM_SUPPORTED = 1'b1;
 localparam logic [63:0] UNCORE_RAM_BASE =       64'h80000000;
-localparam logic [63:0] UNCORE_RAM_RANGE =      64'h07FFFFFF;
+localparam logic [63:0] UNCORE_RAM_RANGE =      64'h0FFFFFFF;
 localparam UNCORE_RAM_PRELOAD = 1'b1;
 localparam EXT_MEM_SUPPORTED = 1'b0;
 localparam logic [63:0] EXT_MEM_BASE =       64'h80000000;

src/cache/cache.sv

@@ -35,7 +35,6 @@ module cache import cvw::*; #(parameter cvw_t P,
   input  logic                   FlushStage,        // Pipeline flush of second stage (prevent writes and bus operations)
   // cpu side
   input  logic [1:0]             CacheRW,           // [1] Read, [0] Write 
-  input  logic [1:0]             CacheAtomic,       // Atomic operation
   input  logic                   FlushCache,        // Flush all dirty lines back to memory
   input  logic                   InvalidateCache,   // Clear all valid bits
   input  logic [3:0]             CMOp,              // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
@@ -90,18 +89,16 @@ module cache import cvw::*; #(parameter cvw_t P,
   logic [NUMWAYS-1:0]            FlushWay, NextFlushWay;
   logic                          FlushWayCntEn;
   logic                          SelWriteback;
-  logic                          SelCMOWriteback;
-  logic                          SelBothWriteback;
   logic                          LRUWriteEn;
   logic                          SelFlush;
   logic                          ResetOrFlushCntRst;
   logic [LINELEN-1:0]            ReadDataLine, ReadDataLineCache;
   logic                          SelFetchBuffer;
   logic                          CacheEn;
+  logic                          SelWay;
   logic [LINELEN/8-1:0]          LineByteMask;
   logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0] WordOffsetAddr;
   logic                                                   ZeroCacheLine;
-  logic                                                   CMOZeroHit;
   logic [LINELEN-1:0]                                     PreLineWriteData;
   genvar                         index;
   
@@ -119,15 +116,15 @@ module cache import cvw::*; #(parameter cvw_t P,
 
   // Array of cache ways, along with victim, hit, dirty, and read merging logic
   cacheway #(P, PA_BITS, XLEN, NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0](
-    .clk, .reset, .CacheEn, .CMOp, .CacheSet, .PAdr, .LineWriteData, .LineByteMask,
+    .clk, .reset, .CacheEn, .CacheSet, .PAdr, .LineWriteData, .LineByteMask, .SelWay,
-    .SetValid, .ClearValid, .SetDirty, .ClearDirty, .CMOZeroHit, .SelWriteback, .SelCMOWriteback, .VictimWay,
+    .SetValid, .ClearValid, .SetDirty, .ClearDirty, .VictimWay,
     .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .TagWay, .FlushStage, .InvalidateCache);
 
   // Select victim way for associative caches
   if(NUMWAYS > 1) begin:vict
     cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cacheLRU(
       .clk, .reset, .FlushStage, .CacheEn, .HitWay, .ValidWay, .VictimWay, .CacheSet, .LRUWriteEn,
-      .SetValid, .ClearValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache, .FlushCache);
+      .SetValid, .ClearValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache);
   end else 
     assign VictimWay = 1'b1; // one hot.
 
@@ -156,11 +153,10 @@ module cache import cvw::*; #(parameter cvw_t P,
     .PAdr(WordOffsetAddr), .ReadDataLine, .ReadDataWord);
   
   // Bus address for fetch, writeback, or flush writeback
-  assign SelBothWriteback = SelWriteback | SelCMOWriteback;
   mux3 #(PA_BITS) CacheBusAdrMux(.d0({PAdr[PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
     .d1({Tag, PAdr[SETTOP-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
     .d2({Tag, FlushAdr, {OFFSETLEN{1'b0}}}),
-    .s({SelFlush, SelBothWriteback}), .y(CacheBusAdr));
+    .s({SelFlush, SelWriteback}), .y(CacheBusAdr));
   
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Write Path
@@ -171,7 +167,6 @@ module cache import cvw::*; #(parameter cvw_t P,
     assign PreLineWriteData = FetchBuffer;
   end
   if(!READ_ONLY_CACHE) begin:WriteSelLogic
-    logic [CACHEWORDSPERLINE-1:0]  MemPAdrDecoded;
     logic [LINELEN/8-1:0]          DemuxedByteMask, FetchBufferByteSel;
 
     // Adjust byte mask from word to cache line
@@ -229,10 +224,10 @@ module cache import cvw::*; #(parameter cvw_t P,
   /////////////////////////////////////////////////////////////////////////////////////////////
   
   cachefsm #(P, READ_ONLY_CACHE) cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck, 
-    .FlushStage, .CacheRW, .CacheAtomic, .Stall,
+    .FlushStage, .CacheRW, .Stall,
     .CacheHit, .LineDirty, .CacheStall, .CacheCommitted, 
-    .CacheMiss, .CacheAccess, .SelAdr, 
+    .CacheMiss, .CacheAccess, .SelAdr, .SelWay,
-    .ClearDirty, .SetDirty, .SetValid, .ClearValid, .ZeroCacheLine, .CMOZeroHit, .SelWriteback, .SelCMOWriteback, .SelFlush,
+    .ClearDirty, .SetDirty, .SetValid, .ClearValid, .ZeroCacheLine, .SelWriteback, .SelFlush,
     .FlushAdrCntEn, .FlushWayCntEn, .FlushCntRst,
     .FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelFetchBuffer,
     .InvalidateCache, .CMOp, .CacheEn, .LRUWriteEn);

src/cache/cacheLRU.sv

@@ -41,7 +41,6 @@ module cacheLRU
   input  logic                SetValid,        // Set the dirty bit in the selected way and set
   input  logic                ClearValid,      // Clear the dirty bit in the selected way and set
   input  logic                InvalidateCache, // Clear all valid bits
-  input  logic                FlushCache,      // Flush all dirty lines back to memory
   output logic [NUMWAYS-1:0]  VictimWay        // LRU selects a victim to evict
 );
 

src/cache/cachefsm.sv

@@ -38,7 +38,6 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
   output logic       CacheStall,        // Cache stalls pipeline during multicycle operation
   // inputs from IEU
   input  logic [1:0] CacheRW,           // [1] Read, [0] Write 
-  input  logic [1:0] CacheAtomic,       // Atomic operation
   input  logic       FlushCache,        // Flush all dirty lines back to memory
   input  logic       InvalidateCache,   // Clear all valid bits
   input  logic [3:0] CMOp,              // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
@@ -60,11 +59,10 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
   output logic       SetDirty,          // Set the dirty bit in the selected way and set
   output logic       ClearDirty,        // Clear the dirty bit in the selected way and set
   output logic       ZeroCacheLine,     // Write zeros to all bytes of cacheline
-  output logic       CMOZeroHit,        // CMOZ hit
   output logic       SelWriteback,      // Overrides cached tag check to select a specific way and set for writeback
-  output logic       SelCMOWriteback,   // Overrides cached tag check to select a specific way and set for writeback for both data and tag
   output logic       LRUWriteEn,        // Update the LRU state
   output logic       SelFlush,          // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr
+  output logic       SelWay,            // Controls which way to select a way data and tag, 00 = hitway, 10 = victimway, 11 = flushway
   output logic       FlushAdrCntEn,     // Enable the counter for Flush Adr
   output logic       FlushWayCntEn,     // Enable the way counter during a flush
   output logic       FlushCntRst,       // Reset both flush counters
@@ -77,6 +75,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
   logic              AnyMiss;
   logic              FlushFlag;
   logic              CMOWritebackHit;
+  logic              CMOWriteback;
   logic              CMOZeroNoEviction;
   logic              CMOZeroEviction;
 
@@ -88,10 +87,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
                            STATE_READ_HOLD,  // required for back to back reads. structural hazard on writting SRAM
                            // flush cache 
                            STATE_FLUSH,
-                           STATE_FLUSH_WRITEBACK,
+                           STATE_FLUSH_WRITEBACK
-                           // CMO states
-                           STATE_CMO_WRITEBACK,
-                           STATE_CMO_DONE
                            } statetype;
 
   statetype CurrState, NextState;
@@ -102,6 +98,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
   assign CMOWritebackHit = (CMOp[1] | CMOp[2]) & CacheHit;
   assign CMOZeroNoEviction = CMOp[3] & ~LineDirty;   // (hit or miss) with no writeback store zeros now
   assign CMOZeroEviction = CMOp[3] & LineDirty;   // (hit or miss) with writeback dirty line
+  assign CMOWriteback = CMOWritebackHit | CMOZeroEviction;
   
   assign FlushFlag = FlushAdrFlag & FlushWayFlag;
 
@@ -124,8 +121,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
       STATE_READY:           if(InvalidateCache)                               NextState = STATE_READY;     // exclusion-tag: dcache InvalidateCheck
                              else if(FlushCache & ~READ_ONLY_CACHE)            NextState = STATE_FLUSH;
                              else if(AnyMiss & (READ_ONLY_CACHE | ~LineDirty)) NextState = STATE_FETCH;     // exclusion-tag: icache FETCHStatement
-                             else if(AnyMiss | CMOZeroEviction)                NextState = STATE_WRITEBACK; // exclusion-tag: icache WRITEBACKStatement
+                             else if(AnyMiss | CMOWriteback)                   NextState = STATE_WRITEBACK; // exclusion-tag: icache WRITEBACKStatement
-                             else if(CMOWritebackHit)                          NextState = STATE_CMO_WRITEBACK; 
                              else                                              NextState = STATE_READY;
       STATE_FETCH:           if(CacheBusAck)                                   NextState = STATE_WRITE_LINE;
                              else if(CacheBusAck)                              NextState = STATE_READY;
@@ -134,8 +130,9 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
       STATE_READ_HOLD:       if(Stall)                                         NextState = STATE_READ_HOLD;
                              else                                              NextState = STATE_READY;
       // exclusion-tag-start: icache case
-      STATE_WRITEBACK:       if(CacheBusAck & ~CMOp[3])                        NextState = STATE_FETCH;
+      STATE_WRITEBACK:       if (CacheBusAck & (CMOp[1] | CMOp[2]))            NextState = STATE_READ_HOLD;
-                             else if(CacheBusAck)                              NextState = STATE_CMO_DONE;
+                             else if(CacheBusAck & ~CMOp[3])                   NextState = STATE_FETCH;
+                             else if(CacheBusAck)                              NextState = STATE_READ_HOLD;
                              else                                              NextState = STATE_WRITEBACK;
       // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack.
       STATE_FLUSH:           if(LineDirty)                                     NextState = STATE_FLUSH_WRITEBACK;
@@ -144,32 +141,25 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
       STATE_FLUSH_WRITEBACK: if(CacheBusAck & ~FlushFlag)                      NextState = STATE_FLUSH;
                              else if(CacheBusAck)                              NextState = STATE_READ_HOLD;
                              else                                              NextState = STATE_FLUSH_WRITEBACK;
-
-      STATE_CMO_WRITEBACK:   if(CacheBusAck & (CMOp[1] | CMOp[2]))             NextState = STATE_CMO_DONE;
-                             else                                              NextState = STATE_CMO_WRITEBACK;
-      STATE_CMO_DONE:        if(Stall)                                         NextState = STATE_CMO_DONE;
-                             else                                              NextState = STATE_READY;
       // exclusion-tag-end: icache case
       default:                                                                 NextState = STATE_READY;
     endcase
   end
 
   // com back to CPU
-  assign CacheCommitted = (CurrState != STATE_READY) & ~(READ_ONLY_CACHE & (CurrState == STATE_READ_HOLD | CurrState == STATE_CMO_DONE));
+  assign CacheCommitted = (CurrState != STATE_READY) & ~(READ_ONLY_CACHE & (CurrState == STATE_READ_HOLD));
-  assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss | CMOWritebackHit | CMOZeroEviction)) | // exclusion-tag: icache StallStates
+  assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss | CMOWriteback)) | // exclusion-tag: icache StallStates
                       (CurrState == STATE_FETCH) |
                       (CurrState == STATE_WRITEBACK) |
                       (CurrState == STATE_WRITE_LINE) |  // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write.
                       (CurrState == STATE_FLUSH) |
-                      (CurrState == STATE_FLUSH_WRITEBACK) |
+                      (CurrState == STATE_FLUSH_WRITEBACK);
-                      (CurrState == STATE_CMO_WRITEBACK);
   // write enables internal to cache
-  assign CMOZeroHit = CurrState == STATE_READY & CMOp[3] & CacheHit ;
   assign SetValid = CurrState == STATE_WRITE_LINE | 
-                    (CurrState == STATE_READY & CMOZeroNoEviction) |
+                    (P.ZICBOZ_SUPPORTED & CurrState == STATE_READY & CMOZeroNoEviction) |
                     (P.ZICBOZ_SUPPORTED & CurrState == STATE_WRITEBACK & CacheBusAck & CMOp[3]); 
   assign ClearValid = P.ZICBOM_SUPPORTED & ((CurrState == STATE_READY & CMOp[0] & CacheHit) |
-                      (CurrState == STATE_CMO_WRITEBACK & CMOp[2] & CacheBusAck));
+                      (CurrState == STATE_WRITEBACK & CMOp[2] & CacheBusAck));
   // coverage off -item e 1 -fecexprrow 8
   assign LRUWriteEn = (((CurrState == STATE_READY & (AnyHit | CMOZeroNoEviction)) |
                        (CurrState == STATE_WRITE_LINE)) & ~FlushStage) |
@@ -181,13 +171,14 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
   assign ClearDirty = (CurrState == STATE_WRITE_LINE & ~(CacheRW[0])) |   // exclusion-tag: icache ClearDirty
                       (CurrState == STATE_FLUSH & LineDirty) | // This is wrong in a multicore snoop cache protocal.  Dirty must be cleared concurrently and atomically with writeback.  For single core cannot clear after writeback on bus ack and change flushadr.  Clears the wrong set.
   // Flush and eviction controls
-                      (P.ZICBOM_SUPPORTED & CurrState == STATE_CMO_WRITEBACK & (CMOp[1] | CMOp[2]) & CacheBusAck);
+                      (P.ZICBOM_SUPPORTED & CurrState == STATE_WRITEBACK & (CMOp[1] | CMOp[2]) & CacheBusAck);
+  assign SelWay = (CurrState == STATE_WRITEBACK & ((~CacheBusAck & ~(CMOp[1] | CMOp[2])) | (P.ZICBOZ_SUPPORTED & CacheBusAck & CMOp[3]))) |
+                  (CurrState == STATE_READY & ((AnyMiss & LineDirty) | (P.ZICBOZ_SUPPORTED & CMOZeroNoEviction & ~CacheHit))) | 
+                  (CurrState == STATE_WRITE_LINE);
   assign ZeroCacheLine = P.ZICBOZ_SUPPORTED & ((CurrState == STATE_READY & CMOZeroNoEviction) | 
                                                (CurrState == STATE_WRITEBACK & (CMOp[3] & CacheBusAck)));  
-  assign SelWriteback = (CurrState == STATE_WRITEBACK & ~CacheBusAck) |
+  assign SelWriteback = (CurrState == STATE_WRITEBACK & (CMOp[1] | CMOp[2] | ~CacheBusAck)) |
                         (CurrState == STATE_READY & AnyMiss & LineDirty);
-  assign SelCMOWriteback = CurrState == STATE_CMO_WRITEBACK;
-
   assign SelFlush = (CurrState == STATE_READY & FlushCache) |
           (CurrState == STATE_FLUSH) | 
           (CurrState == STATE_FLUSH_WRITEBACK);
@@ -203,17 +194,16 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
   // Bus interface controls
   assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss & ~LineDirty) | // exclusion-tag: icache CacheBusRCauses
                          (CurrState == STATE_FETCH & ~CacheBusAck) | 
-                         (CurrState == STATE_WRITEBACK & CacheBusAck & ~CMOp[3]);
+                         (CurrState == STATE_WRITEBACK & CacheBusAck & ~(|CMOp));
   assign CacheBusRW[0] = (CurrState == STATE_READY & AnyMiss & LineDirty) | // exclusion-tag: icache CacheBusW
                          (CurrState == STATE_WRITEBACK & ~CacheBusAck) |
                          (CurrState == STATE_FLUSH_WRITEBACK & ~CacheBusAck) |
-                         (P.ZICBOM_SUPPORTED & CurrState == STATE_CMO_WRITEBACK & (CMOp[1] | CMOp[2]) & ~CacheBusAck);
+                         (P.ZICBOM_SUPPORTED & CurrState == STATE_WRITEBACK & (CMOp[1] | CMOp[2]) & ~CacheBusAck);
 
   assign SelAdr = (CurrState == STATE_READY & (CacheRW[0] | AnyMiss | (|CMOp))) | // exclusion-tag: icache SelAdrCauses // changes if store delay hazard removed
                   (CurrState == STATE_FETCH) |
                   (CurrState == STATE_WRITEBACK) |
                   (CurrState == STATE_WRITE_LINE) |
-                  (CurrState == STATE_CMO_WRITEBACK) |
                   resetDelay;
   assign SelFetchBuffer = CurrState == STATE_WRITE_LINE | CurrState == STATE_READ_HOLD;
   assign CacheEn = (~Stall | FlushCache | AnyMiss) | (CurrState != STATE_READY) | reset | InvalidateCache; // exclusion-tag: dcache CacheEn

src/cache/cacheway.sv

@@ -33,7 +33,6 @@ module cacheway import cvw::*; #(parameter cvw_t P,
   input  logic                        clk,
   input  logic                        reset,
   input  logic                        FlushStage,     // Pipeline flush of second stage (prevent writes and bus operations)
-  input  logic [3:0]                  CMOp,           // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
   input  logic                        CacheEn,        // Enable the cache memory arrays.  Disable hold read data constant
   input  logic [$clog2(NUMLINES)-1:0] CacheSet,       // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
   input  logic [PA_BITS-1:0]          PAdr,           // Physical address 
@@ -41,10 +40,8 @@ module cacheway import cvw::*; #(parameter cvw_t P,
   input  logic                        SetValid,       // Set the valid bit in the selected way and set
   input  logic                        ClearValid,     // Clear the valid bit in the selected way and set
   input  logic                        SetDirty,       // Set the dirty bit in the selected way and set
-  input  logic                        CMOZeroHit,  // Write zeros to all bytes of a cache line
+  input  logic                        SelWay,         // Controls which way to select a way data and tag, 00 = hitway, 10 = victimway, 11 = flushway
   input  logic                        ClearDirty,     // Clear the dirty bit in the selected way and set
-  input  logic                        SelWriteback,   // Overrides cached tag check to select a specific way and set for writeback
-  input  logic                        SelCMOWriteback,// Overrides cached tag check to select a specific way and set for writeback for both data and tag
   input  logic                        SelFlush,       // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr
   input  logic                        VictimWay,      // LRU selected this way as victim to evict
   input  logic                        FlushWay,       // This way is selected for flush and possible writeback if dirty
@@ -78,32 +75,19 @@ module cacheway import cvw::*; #(parameter cvw_t P,
   logic                               ClearDirtyWay;
   logic                               SelNonHit;
   logic                               SelData;
-  logic                               SelNotHit2;
-  
-  if (P.ZICBOZ_SUPPORTED) begin : cbologic
-    assign SelNotHit2 = SetValid & ~CMOZeroHit;
-    //assign SelNotHit2 = SetValid;
-    
-  end else begin : cbologic
-    assign SelNotHit2 = SetValid;
-  end
   
   if (!READ_ONLY_CACHE) begin:flushlogic
     logic                               FlushWayEn;
-
     mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag);
 
     // FlushWay is part of a one hot way selection. Must clear it if FlushWay not selected.
     // coverage off -item e 1 -fecexprrow 3
     // nonzero ways will never see SelFlush=0 while FlushWay=1 since FlushWay only advances on a subset of SelFlush assertion cases.
     assign FlushWayEn = FlushWay & SelFlush;
-    // *** RT: This is slopy. I should refactor to have the fsm issue two types of writeback commands
+    assign SelNonHit = FlushWayEn | SelWay; 
-    assign SelNonHit = FlushWayEn | SelNotHit2 | SelWriteback; // *** this is not correct
-
-    //assign SelNonHit = FlushWayEn | SelNotHit2 | SelWriteback;
   end else begin:flushlogic // no flush operation for read-only caches.
     assign SelTag = VictimWay;
-    assign SelNonHit = SelNotHit2;
+    assign SelNonHit = SelWay;
   end
 
   mux2 #(1) selectedwaymux(HitWay, SelTag, SelNonHit , SelData);

src/ebu/ebu.sv

@@ -52,7 +52,7 @@ module ebu #(parameter XLEN, PA_BITS, AHBW)(
   // AHB-Lite external signals
   output logic                HCLK, HRESETn, 
   input  logic                HREADY,    // AHB peripheral ready
-  input  logic                HRESP,     // AHB peripheral response. 0: OK 1: Error
+  input  logic                HRESP,     // AHB peripheral response. 0: OK 1: Error.  Presently ignored.
   output logic [PA_BITS-1:0]  HADDR,     // AHB address to peripheral after arbitration
   output logic [AHBW-1:0]     HWDATA,    // AHB Write data after arbitration
   output logic [XLEN/8-1:0]   HWSTRB,    // AHB byte write enables after arbitration

src/fpu/fctrl.sv

@@ -41,7 +41,7 @@ module fctrl import cvw::*;  #(parameter cvw_t P) (
   input  logic [6:0]           Funct7D,                            // bits 31:25 of instruction - may contain percision
   input  logic [6:0]           OpD,                                // bits 6:0 of instruction
   input  logic [4:0]           Rs2D,                               // bits 24:20 of instruction
-  input  logic [2:0]           Funct3D, Funct3E,                   // bits 14:12 of instruction - may contain rounding mode
+  input  logic [2:0]           Funct3D,                            // bits 14:12 of instruction - may contain rounding mode
   // input mux selections                                         
   output logic                 XEnD, YEnD, ZEnD,                   // enable inputs
   output logic                 XEnE, YEnE, ZEnE,                   // enable inputs

src/fpu/fdivsqrt/fdivsqrtexpcalc.sv

@@ -30,7 +30,6 @@ module fdivsqrtexpcalc import cvw::*;  #(parameter cvw_t P) (
   input  logic [P.FMTBITS-1:0] Fmt,
   input  logic [P.NE-1:0]      Xe, Ye,    // input exponents
   input  logic                 Sqrt,
-  input  logic                 XZero, 
  input  logic [P.DIVBLEN-1:0] ell, m,    // number of leading 0s in Xe and Ye
   output logic [P.NE+1:0]      Ue         // result exponent
   );

src/fpu/fdivsqrt/fdivsqrtpreproc.sv

@@ -210,7 +210,7 @@ module fdivsqrtpreproc import cvw::*;  #(parameter cvw_t P) (
   flopen #(P.DIVb+4) dreg(clk, IFDivStartE, {3'b000, Dnorm}, D);
  
   // Floating-point exponent
-  fdivsqrtexpcalc #(P) expcalc(.Fmt(FmtE), .Xe, .Ye, .Sqrt(SqrtE), .XZero(XZeroE), .ell, .m(mE), .Ue(UeE));
+  fdivsqrtexpcalc #(P) expcalc(.Fmt(FmtE), .Xe, .Ye, .Sqrt(SqrtE), .ell, .m(mE), .Ue(UeE));
   flopen #(P.NE+2) expreg(clk, IFDivStartE, UeE, UeM);
 
   // Number of FSM cycles (to FSM)

src/fpu/fpu.sv

@@ -167,7 +167,7 @@ module fpu import cvw::*;  #(parameter cvw_t P) (
 
   // calculate FP control signals
   fctrl #(P) fctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]), 
-              .Funct3E, .IntDivE, .InstrD,
+              .IntDivE, .InstrD,
               .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW, .FRM_REGW, .STATUS_FS, .FDivBusyE,
               .reset, .clk, .FRegWriteE, .FRegWriteM, .FRegWriteW, .FrmM, .FmtE, .FmtM,
               .FDivStartE, .IDivStartE, .FWriteIntE, .FCvtIntE, .FWriteIntM, .OpCtrlE, .OpCtrlM, .FpLoadStoreM,

src/hazard/hazard.sv

@@ -32,7 +32,6 @@ module hazard import cvw::*;  #(parameter cvw_t P) (
   input  logic  LSUStallM, IFUStallF,
   input  logic  FCvtIntStallD, FPUStallD,
   input  logic  DivBusyE, FDivBusyE,
-  input  logic  EcallFaultM, BreakpointFaultM,
   input  logic  wfiM, IntPendingM,
   // Stall & flush outputs
   output logic StallF, StallD, StallE, StallM, StallW,

src/ieu/alu.sv

@@ -45,7 +45,6 @@ module alu import cvw::*; #(parameter cvw_t P, parameter WIDTH) (
   logic [WIDTH-1:0] CondMaskInvB, Shift, FullResult, PreALUResult;                // Intermediate Signals 
   logic [WIDTH-1:0] CondMaskB;                                                    // Result of B mask select mux
   logic [WIDTH-1:0] CondShiftA;                                                   // Result of A shifted select mux
-  logic [WIDTH-1:0] CondExtA;                                                     // Result of Zero Extend A select mux
   logic             Carry, Neg;                                                   // Flags: carry out, negative
   logic             LT, LTU;                                                      // Less than, Less than unsigned
   logic             Asign, Bsign;                                                 // Sign bits of A, B

src/ieu/controller.sv

@@ -103,7 +103,6 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   logic        BaseRegWriteD;                  // Indicates if Base instruction register write instruction
   logic        BaseSubArithD;                  // Indicates if Base instruction subtracts, sra, slt, sltu
   logic        BaseALUSrcBD;                   // Base instruction ALU B source select signal
-  logic [2:0]  ALUControlD;                    // Determines ALU operation
   logic        ALUSrcAD, ALUSrcBD;             // ALU inputs
   logic        ALUResultSrcD, W64D, MDUD;      // ALU result, is RV64 W-type, is multiply/divide instruction
   logic        CSRZeroSrcD;                    // Ignore setting and clearing zeros to CSR
@@ -118,7 +117,6 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   logic [`CTRLW-1:0] ControlsD;                // Main Instruction Decoder control signals
   logic        SubArithD;                      // TRUE for R-type subtracts and sra, slt, sltu or B-type ext clr, andn, orn, xnor
   logic        subD, sraD, sltD, sltuD;        // Indicates if is one of these instructions
-  logic        ALUOpE;                         // 0 for address generationm 1 for ALU operations
   logic        BranchTakenE;                   // Branch is taken
   logic        eqE, ltE;                       // Comparator outputs
   logic        unused; 

src/ifu/ifu.sv

@@ -33,7 +33,7 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   // Command from CPU
   input  logic                 InvalidateICacheM,                        // Clears all instruction cache valid bits
   input  logic                 CSRWriteFenceM,                           // CSR write or fence instruction, PCNextF = the next valid PC (typically PCE)
-  input  logic                 InstrValidD, InstrValidE, InstrValidM,
+  input  logic                 InstrValidD, InstrValidE, 
   input  logic                 BranchD, BranchE,
   input  logic                 JumpD, JumpE,
   // Bus interface
@@ -103,7 +103,6 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   logic                        BranchMisalignedFaultE;                   // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
   logic [P.XLEN-1:0]           PCPlus2or4F;                              // PCF + 2 (CompressedF) or PCF + 4 (Non-compressed)
   logic [P.XLEN-1:0]           PCSpillNextF;                             // Next PCF after possible + 2 to handle spill
-  logic [P.XLEN-1:0]           PCLinkD;                                  // PCF2or4F delayed 1 cycle.  This is next PC after a control flow instruction (br or j)
   logic [P.XLEN-1:2]           PCPlus4F;                                 // PCPlus4F is always PCF + 4.  Fancy way to compute PCPlus2or4F
   logic [P.XLEN-1:0]           PCD;                                      // Decode stage instruction address
   logic [P.XLEN-1:0]           NextValidPCE;                             // The PC of the next valid instruction in the pipeline after  csr write or fence
@@ -228,7 +227,6 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
       logic [P.PA_BITS-1:0] ICacheBusAdr;
       logic                 ICacheBusAck;
       logic [1:0]           CacheBusRW, BusRW, CacheRWF;
-      logic [1:0]           CacheBusRWTemp;
       
       assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : '0;
       assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0;
@@ -246,7 +244,7 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
              .ByteMask('0), .BeatCount('0), .SelBusBeat('0),
              .CacheWriteData('0),
              .CacheRW(CacheRWF), 
-             .CacheAtomic('0), .FlushCache('0),
+             .FlushCache('0),
              .NextSet(PCSpillNextF[11:0]),
              .PAdr(PCPF),
              .CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM), .CMOp('0)); 

src/lsu/lsu.sv

@@ -40,7 +40,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
   input  logic [1:0]              AtomicM,                              // Atomic memory operation
   input  logic                    FlushDCacheM,                         // Flush D cache to next level of memory
   input  logic [3:0]              CMOpM,                                // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
-  input  logic                    LSUPrefetchM,                         // Prefetch
+  input  logic                    LSUPrefetchM,                         // Prefetch; presently unused
   output logic                    CommittedM,                           // Delay interrupts while memory operation in flight
   output logic                    SquashSCW,                            // Store conditional failed disable write to GPR
   output logic                    DCacheMiss,                           // D cache miss for performance counters
@@ -291,7 +291,6 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
       logic [1:0]              BusRW;                                            // Uncached bus memory access
       logic                    CacheableOrFlushCacheM;                           // Memory address is cacheable or operation is a cache flush
       logic [1:0]              CacheRWM;                                         // Cache read (10), write (01), AMO (11)
-      logic [1:0]              CacheAtomicM;                                     // Cache AMO
       logic                    FlushDCache;                                      // Suppress d cache flush if there is an ITLB miss.
       logic                    CacheStall;
       logic [1:0]              CacheBusRWTemp;
@@ -299,12 +298,11 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
       assign BusRW = ~CacheableM & ~SelDTIM ? LSURWM : '0;
       assign CacheableOrFlushCacheM = CacheableM | FlushDCacheM;
       assign CacheRWM = CacheableM & ~SelDTIM ? LSURWM : '0;
-      assign CacheAtomicM = CacheableM & ~SelDTIM ? LSUAtomicM : '0;
       assign FlushDCache = FlushDCacheM & ~(SelHPTW);
       
       cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMLINES(P.DCACHE_WAYSIZEINBYTES*8/LINELEN),
               .NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(CACHEWORDLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache(
-        .clk, .reset, .Stall(GatedStallW & ~SelSpillE), .SelBusBeat, .FlushStage(FlushW | IgnoreRequestTLB), .CacheRW(SelStoreDelay ? 2'b00 : CacheRWM), .CacheAtomic(CacheAtomicM),
+        .clk, .reset, .Stall(GatedStallW & ~SelSpillE), .SelBusBeat, .FlushStage(FlushW | IgnoreRequestTLB), .CacheRW(SelStoreDelay ? 2'b00 : CacheRWM), 
         .FlushCache(FlushDCache), .NextSet(IEUAdrExtE[11:0]), .PAdr(PAdrM), 
         .ByteMask(ByteMaskSpillM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]),
         .CacheWriteData(LSUWriteDataSpillM), .SelHPTW,

src/privileged/csr.sv

@@ -38,8 +38,7 @@ module csr import cvw::*;  #(parameter cvw_t P) (
   input  logic [P.XLEN-1:0]        SrcAM, IEUAdrM,            // SrcA and memory address from IEU
   input  logic                     CSRReadM, CSRWriteM,       // read or write CSR
   input  logic                     TrapM,                     // trap is occurring
-  input  logic                     mretM, sretM, wfiM,        // return or WFI instruction
+  input  logic                     mretM, sretM,              // return instruction
-  input  logic                     IntPendingM,               // at least one interrupt is pending and could occur if enabled
   input  logic                     InterruptM,                // interrupt is occurring
   input  logic                     ExceptionM,                // interrupt is occurring
   input  logic                     MTimerInt,                 // timer interrupt
@@ -248,7 +247,7 @@ module csr import cvw::*;  #(parameter cvw_t P) (
     csrs #(P) csrs(.clk, .reset,
       .CSRSWriteM, .STrapM, .CSRAdrM,
       .NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW, 
-      .STATUS_TVM, .MCOUNTEREN_TM(MCOUNTEREN_REGW[1]),
+      .STATUS_TVM, 
       .CSRWriteValM, .PrivilegeModeW,
       .CSRSReadValM, .STVEC_REGW, .SEPC_REGW,      
       .SCOUNTEREN_REGW,

src/privileged/csrm.sv

@@ -60,7 +60,7 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
 
   // Machine CSRs
   localparam MVENDORID     = 12'hF11;
-  localparam MARCHID       = 12'hF12;
+  localparam MARCHID       = 12'hF12; // github.com/riscv/riscv-isa-manual/blob/main/marchid.md
   localparam MIMPID        = 12'hF13;
   localparam MHARTID       = 12'hF14;
   localparam MCONFIGPTR    = 12'hF15;
@@ -216,8 +216,8 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
     end
     else case (CSRAdrM) 
       MISA_ADR:      CSRMReadValM = MISA_REGW;
-      MVENDORID:     CSRMReadValM = 0;
+      MVENDORID:     CSRMReadValM = {{(P.XLEN-32){1'b0}}, 32'h0000_0602}; // OpenHW JEDEC
-      MARCHID:       CSRMReadValM = 0;
+      MARCHID:       CSRMReadValM = {{(P.XLEN-32){1'b0}}, 32'h24}; // 36 for CV-Wally 
       MIMPID:        CSRMReadValM = {{P.XLEN-12{1'b0}}, 12'h100}; // pipelined implementation
       MHARTID:       CSRMReadValM = MHARTID_REGW; // hardwired to 0 
       MCONFIGPTR:    CSRMReadValM = 0; // hardwired to 0

src/privileged/csrs.sv

@@ -35,7 +35,6 @@ module csrs import cvw::*;  #(parameter cvw_t P) (
   input  logic [P.XLEN-1:0] NextEPCM, NextMtvalM, SSTATUS_REGW, 
   input  logic [4:0]        NextCauseM,
   input  logic              STATUS_TVM,
-  input  logic              MCOUNTEREN_TM, // TM bit (1) of MCOUNTEREN; cause illegal instruction when trying to access STIMECMP if clear
   input  logic [P.XLEN-1:0] CSRWriteValM,
   input  logic [1:0]        PrivilegeModeW,
   output logic [P.XLEN-1:0] CSRSReadValM, STVEC_REGW,

src/privileged/privdec.sv

@@ -29,7 +29,7 @@
 
 module privdec import cvw::*;  #(parameter cvw_t P) (
   input  logic         clk, reset,
-  input  logic         StallM, StallW, FlushW, 
+  input  logic         StallW, FlushW, 
   input  logic [31:15] InstrM,                              // privileged instruction function field
   input  logic         PrivilegedM,                         // is this a privileged instruction (from IEU controller)
   input  logic         IllegalIEUFPUInstrM,                 // Not a legal IEU instruction

src/privileged/privileged.sv

@@ -93,7 +93,6 @@ module privileged import cvw::*;  #(parameter cvw_t P) (
   input  logic              InvalidateICacheM,                              // fence instruction
   output logic              BigEndianM,                                     // Use big endian in current privilege mode
   // Fault outputs                                                         
-  output logic              BreakpointFaultM, EcallFaultM,                  // breakpoint and Ecall traps should retire
   output logic              wfiM, IntPendingM                               // Stall in Memory stage for WFI until interrupt pending or timeout
 );                                                                         
                                                                            
@@ -114,6 +113,7 @@ module privileged import cvw::*;  #(parameter cvw_t P) (
   logic                     InterruptM;                                     // interrupt occuring
   logic                     ExceptionM;                                     // Memory stage instruction caused a fault
   logic                     HPTWInstrAccessFaultM;                          // Hardware page table access fault while fetching instruction PTE
+  logic                     BreakpointFaultM, EcallFaultM;                  // breakpoint and Ecall traps should retire
   
   logic                     wfiW;
   
@@ -122,7 +122,7 @@ module privileged import cvw::*;  #(parameter cvw_t P) (
     .STATUS_MPP, .STATUS_SPP, .NextPrivilegeModeM, .PrivilegeModeW);
 
   // decode privileged instructions
-  privdec #(P) pmd(.clk, .reset, .StallM, .StallW, .FlushW, .InstrM(InstrM[31:15]), 
+  privdec #(P) pmd(.clk, .reset, .StallW, .FlushW, .InstrM(InstrM[31:15]), 
     .PrivilegedM, .IllegalIEUFPUInstrM, .IllegalCSRAccessM, 
     .PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .IllegalInstrFaultM, 
     .EcallFaultM, .BreakpointFaultM, .sretM, .mretM, .wfiM, .wfiW, .sfencevmaM);
@@ -130,7 +130,7 @@ module privileged import cvw::*;  #(parameter cvw_t P) (
   // Control and Status Registers
   csr #(P) csr(.clk, .reset, .FlushM, .FlushW, .StallE, .StallM, .StallW,
     .InstrM, .InstrOrigM, .PCM, .SrcAM, .IEUAdrM, .PC2NextF,
-    .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .IntPendingM, .InterruptM,
+    .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .InterruptM,
     .MTimerInt, .MExtInt, .SExtInt, .MSwInt,
     .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD,
     .BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .BPWrongM,

src/uncore/spi_apb.sv

@@ -68,11 +68,10 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
     // Watermark signals - TransmitReadMark = ip[0], ReceiveWriteMark = ip[1]
     logic TransmitWriteMark, TransmitReadMark, RecieveWriteMark, RecieveReadMark; 
     logic TransmitFIFOWriteFull, TransmitFIFOReadEmpty;
-    logic TransmitFIFOReadIncrement;
     logic TransmitFIFOWriteIncrement;
     logic ReceiveFIFOReadIncrement;
     logic ReceiveFIFOWriteFull, ReceiveFIFOReadEmpty;
-    logic [7:0] TransmitFIFOReadData, ReceiveFIFOWriteData;
+    logic [7:0] TransmitFIFOReadData;
     logic [2:0] TransmitWriteWatermarkLevel, ReceiveReadWatermarkLevel;
     logic [7:0] ReceiveShiftRegEndian;              // Reverses ReceiveShiftReg if Format[2] set (little endian transmission)
 
@@ -92,7 +91,6 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
 
     // Frame counting signals
     logic [3:0] FrameCount;                         // Counter for number of frames in transmission
-    logic [3:0] ReceivePenultimateFrameCount;       // Counter
     logic ReceivePenultimateFrame;                  // High when penultimate frame in transmission has been reached
 
     // State fsm signals

src/wally/wallypipelinedcore.sv

@@ -158,7 +158,6 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
   logic                          DCacheAccess;
   logic                          ICacheMiss;
   logic                          ICacheAccess;
-  logic                          BreakpointFaultM, EcallFaultM;
   logic                          InstrUpdateDAF;
   logic                          BigEndianM;
   logic                          FCvtIntE;
@@ -170,7 +169,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
   // instruction fetch unit: PC, branch prediction, instruction cache
   ifu #(P) ifu(.clk, .reset,
     .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-    .InstrValidM, .InstrValidE, .InstrValidD,
+    .InstrValidE, .InstrValidD,
     .BranchD, .BranchE, .JumpD, .JumpE, .ICacheStallF,
     // Fetch
     .HRDATA, .PCSpillF, .IFUHADDR, .PC2NextF,
@@ -270,7 +269,6 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
     .LSUStallM, .IFUStallF,
     .FCvtIntStallD, .FPUStallD,
     .DivBusyE, .FDivBusyE,
-    .EcallFaultM, .BreakpointFaultM,
     .wfiM, .IntPendingM,
     // Stall & flush outputs
     .StallF, .StallD, .StallE, .StallM, .StallW,
@@ -298,7 +296,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
       .PrivilegeModeW, .SATP_REGW,
       .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS, 
       .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, 
-      .FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_HADE, .BreakpointFaultM, .EcallFaultM, .wfiM, .IntPendingM, .BigEndianM);
+      .FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_HADE, .wfiM, .IntPendingM, .BigEndianM);
   end else begin
     assign CSRReadValW      = 0;
     assign UnalignedPCNextF = PC2NextF;

synthDC/ppa/ppaAnalyze.py

@@ -67,6 +67,7 @@ def synthsintocsv():
 
     for oneSynth in allSynths:
         module, width, risc, tech, freq = specReg.findall(oneSynth)[1:6]
+        tech = tech[:-2]  
         metrics = []
         for phrase in [["Path Slack", "qor"], ["Design Area", "qor"], ["100", "power"]]:
             bashCommand = 'grep "{}" ' + oneSynth[2:] + "/reports/*{}*"

testbench/common/wallyTracer.sv

@@ -23,6 +23,7 @@
 `define NUM_REGS 32
 `define NUM_CSRS 4096
 
+`define STD_LOG 1
 `define PRINT_PC_INSTR 0
 `define PRINT_MOST 0
 `define PRINT_ALL 0
@@ -495,8 +496,38 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
 
   integer index2;
 
+  string  instrWName;
+  int     file;
+  string  LogFile;
+  if(`STD_LOG) begin
+    instrNameDecTB NameDecoder(rvvi.insn[0][0], instrWName);
+    initial begin
+      LogFile = "InstrTrace.log";
+      file = $fopen(LogFile, "w");
+    end
+  end
+  
   always_ff @(posedge clk) begin
 	if(rvvi.valid[0][0]) begin
+      if(`STD_LOG) begin
+        $fwrite(file, "%016x, %08x, %s\t\t", rvvi.pc_rdata[0][0], rvvi.insn[0][0], instrWName);
+        for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
+          if(rvvi.x_wb[0][0][index2]) begin
+            $fwrite(file, "rf[%02d] = %016x ", index2, rvvi.x_wdata[0][0][index2]);
+          end
+        end
+        for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
+          if(rvvi.f_wb[0][0][index2]) begin
+            $fwrite(file, "frf[%02d] = %016x ", index2, rvvi.f_wdata[0][0][index2]);
+          end
+        end
+        for(index2 = 0; index2 < `NUM_CSRS; index2 += 1) begin
+          if(rvvi.csr_wb[0][0][index2]) begin
+            $fwrite(file, "csr[%03x] = %016x ", index2, rvvi.csr[0][0][index2]);
+          end
+        end
+        $fwrite(file, "\n");
+      end
 	  if(`PRINT_PC_INSTR & !(`PRINT_ALL | `PRINT_MOST))
 		$display("order = %08d, PC = %08x, insn = %08x", rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0]);
 	  else if(`PRINT_MOST & !`PRINT_ALL)

tests/riscof/spike/spike_rv32gc_isa.yaml

@@ -1,6 +1,6 @@
 hart_ids: [0]
 hart0:
-  ISA: RV32IMAFDCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs
+  ISA: RV32IMAFDCZicsr_Zicboz_Zifencei_Zba_Zbb_Zbc_Zbs
   physical_addr_sz: 32
   User_Spec_Version: '2.3'
   supported_xlen: [32]

tests/riscof/spike/spike_rv64gc_isa.yaml

@@ -1,6 +1,6 @@
 hart_ids: [0]
 hart0:
-  ISA: RV64IMAFDCSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs
+  ISA: RV64IMAFDCSUZicsr_Zicboz_Zifencei_Zba_Zbb_Zbc_Zbs
   physical_addr_sz: 56
   User_Spec_Version: '2.3'
   supported_xlen: [64]