More name cleanup in caches.

wally-pipelined/src/cache/cacheway.sv

@@ -47,7 +47,7 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
    input logic 						  SelFlush,
    input logic 						  FlushWay,
 
-   output logic [BLOCKLEN-1:0] 	      ReadDataBlockWayMasked,
+   output logic [BLOCKLEN-1:0] 		  ReadDataLineWayMasked,
    output logic 					  WayHit,
    output logic 					  VictimDirtyWay,
    output logic [TAGLEN-1:0] 		  VictimTagWay
@@ -93,7 +93,7 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
   assign WayHit = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]);
   assign SelectedWay = SelFlush ? FlushWay : 
 					   SelEvict ? VictimWay : WayHit;  
-  assign ReadDataBlockWayMasked = SelectedWay ? ReadDataBlockWay : '0;  // first part of AO mux.
+  assign ReadDataLineWayMasked = SelectedWay ? ReadDataBlockWay : '0;  // first part of AO mux.
 
   assign VictimDirtyWay = SelFlush ? FlushWay & Dirty & Valid :
 						  VictimWay & Dirty & Valid;

wally-pipelined/src/cache/dcache.sv

@@ -79,10 +79,10 @@ module dcache
   logic [BLOCKLEN-1:0] 						SRAMWriteData;
   logic 									SetValid, ClearValid;
   logic 									SetDirty, ClearDirty;
-  logic [BLOCKLEN-1:0] 						ReadDataBlockWayMaskedM [NUMWAYS-1:0];
+  logic [BLOCKLEN-1:0] 						ReadDataLineWayMasked [NUMWAYS-1:0];
   logic [NUMWAYS-1:0] 						WayHit;
   logic 									CacheHit;
-  logic [BLOCKLEN-1:0] 						ReadDataBlockM;
+  logic [BLOCKLEN-1:0] 						ReadDataLineM;
   logic [WORDSPERLINE-1:0] 					SRAMWordEnable;
 
   logic 									SRAMWordWriteEnableM;
@@ -137,7 +137,7 @@ module dcache
 					  .WriteData(SRAMWriteData),
 					  .SetValid, .ClearValid, .SetDirty, .ClearDirty, .SelEvict,
 					  .VictimWay, .FlushWay, .SelFlush,
-					  .ReadDataBlockWayMasked(ReadDataBlockWayMaskedM),
+					  .ReadDataLineWayMasked,
 					  .WayHit, .VictimDirtyWay, .VictimTagWay,
 					  .InvalidateAll(1'b0));
 
@@ -159,10 +159,10 @@ module dcache
   assign VictimDirty = | VictimDirtyWay;
 
   
-  // ReadDataBlockWayMaskedM is a 2d array of cache block len by number of ways.
+  // ReadDataLineWayMaskedM is a 2d array of cache block len by number of ways.
   // Need to OR together each way in a bitwise manner.
   // Final part of the AO Mux.  First is the AND in the cacheway.
-  or_rows #(NUMWAYS, BLOCKLEN) ReadDataAOMux(.a(ReadDataBlockWayMaskedM), .y(ReadDataBlockM));
+  or_rows #(NUMWAYS, BLOCKLEN) ReadDataAOMux(.a(ReadDataLineWayMasked), .y(ReadDataLineM));
   or_rows #(NUMWAYS, TAGLEN) VictimTagAOMux(.a(VictimTagWay), .y(VictimTag));  
 
 
@@ -172,7 +172,7 @@ module dcache
   genvar index;
   generate
     for (index = 0; index < WORDSPERLINE; index++) begin
-      assign ReadDataBlockSetsM[index] = ReadDataBlockM[((index+1)*`XLEN)-1: (index*`XLEN)];
+      assign ReadDataBlockSetsM[index] = ReadDataLineM[((index+1)*`XLEN)-1: (index*`XLEN)];
     end
   endgenerate
 

wally-pipelined/src/cache/icache.sv

@@ -29,7 +29,7 @@ module icache
   (
    // Basic pipeline stuff
    input logic 				  clk, reset,
-   input logic 		       StallF, 
+   input logic 				  CPUBusy, 
    input logic [`PA_BITS-1:0] PCNextF,
    input logic [`PA_BITS-1:0] PCPF,
    input logic [`XLEN-1:0] 	  PCF,
@@ -46,6 +46,7 @@ module icache
    output logic 			  CompressedF,
    // High if the icache is requesting a stall
    output logic 			  ICacheStallF,
+   input logic 				  CacheableF,
    input logic 				  ITLBMissF,
    input logic 				  ITLBWriteF,
    input logic 				  InvalidateICacheM,
@@ -106,10 +107,9 @@ module icache
   logic 					  hit;
   
   
-  logic [BLOCKLEN-1:0] 	       ReadDataBlockWayMasked [NUMWAYS-1:0];
+  logic [BLOCKLEN-1:0] 		  ReadDataLineWayMasked [NUMWAYS-1:0];
 
 
-  logic 		       CacheableF;
   
   logic [`PA_BITS-1:0] 		  BasePAdrF, BasePAdrMaskedF;
   logic [OFFSETLEN-1:0] 	  BasePAdrOffsetF;
@@ -131,7 +131,6 @@ module icache
 			.y(RAdr));
 
 
-
   cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN), 
 			 .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN), .DIRTY_BITS(0))
   MemWay[NUMWAYS-1:0](.clk, .reset, .RAdr,
@@ -145,7 +144,7 @@ module icache
 					  .ClearValid(1'b0), .SetDirty(1'b0), .ClearDirty(1'b0), .SelEvict(1'b0),
 					  .VictimWay,
 					  .FlushWay(1'b0), .SelFlush(1'b0),
-		      .ReadDataBlockWayMasked, .WayHit,
+					  .ReadDataLineWayMasked, .WayHit,
 					  .VictimDirtyWay(), .VictimTagWay(),
 					  .InvalidateAll(InvalidateICacheM));
   
@@ -157,7 +156,7 @@ module icache
 							 .VictimWay,
 							 .LsuPAdrM(PCTagF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
 							 .RAdr,
-			     .LRUWriteEn); // *** connect
+							 .LRUWriteEn);
     end else begin
       assign VictimWay = 1'b1; // one hot.
     end
@@ -165,10 +164,10 @@ module icache
 
   assign hit = | WayHit;
 
-  // ReadDataBlockWayMasked is a 2d array of cache block len by number of ways.
+  // ReadDataLineWayMasked is a 2d array of cache block len by number of ways.
   // Need to OR together each way in a bitwise manner.
   // Final part of the AO Mux.  First is the AND in the cacheway.
-  or_rows #(NUMWAYS, BLOCKLEN) ReadDataAOMux(.a(ReadDataBlockWayMasked), .y(ReadLineF));
+  or_rows #(NUMWAYS, BLOCKLEN) ReadDataAOMux(.a(ReadDataLineWayMasked), .y(ReadLineF));
   
   
   always_comb begin
@@ -250,17 +249,10 @@ module icache
   assign PCTagF = SelAdr_q[1] ? PCPSpillF : PCPF;
 
   // unlike the dcache the victim is never dirty so no eviction is necessary.
-/* -----\/----- EXCLUDED -----\/-----
-  mux2 #(`PA_BITS) BaseAdrMux(.d0(PCTagF),
-			      .d1({VictimTag, PCTagF[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
-			      .s(SelEvict),
-			      .y(BasePAdrF));
- -----/\----- EXCLUDED -----/\----- */
   assign BasePAdrF = PCTagF;
 
   // if not cacheable the offset bits needs to be sent to the EBU.
   // if cacheable the offset bits are discarded.  $ FSM will fetch the whole block.
-  assign CacheableF = 1'b1; // *** BUG needs to be an input from MMU.
   assign BasePAdrOffsetF = CacheableF ? {{OFFSETLEN}{1'b0}} : BasePAdrF[OFFSETLEN-1:0];
   assign BasePAdrMaskedF = {BasePAdrF[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetF};
   
@@ -272,7 +264,7 @@ module icache
 
   icachefsm  controller(.clk,
 						.reset,
-			.StallF,
+						.CPUBusy,
 						.ICacheReadEn,
 						.ICacheMemWriteEnable,
 						.ICacheStallF,

wally-pipelined/src/cache/icachefsm.sv

@@ -29,7 +29,7 @@ module icachefsm
   (// Inputs from pipeline
    input logic 		  clk, reset,
 
-   input logic 		  StallF,
+   input logic 		  CPUBusy,
 
    // inputs from mmu
    input logic 		  ITLBMissF,
@@ -105,10 +105,6 @@ module icachefsm
 					   STATE_MISS_SPILL_FINAL, // this state replicates STATE_READY's replay of the
 					   // spill access but does nto consider spill.  It also does not do another operation.
 
-					   STATE_INVALIDATE, // *** not sure if invalidate or evict? invalidate by cache block or address?
-					   STATE_TLB_MISS,
-					   STATE_TLB_MISS_DONE,
-
 					   STATE_CPU_BUSY,
 					   STATE_CPU_BUSY_SPILL		
 					   } statetype;
@@ -149,7 +145,7 @@ module icachefsm
 		else if (hit & ~spill) begin
           ICacheStallF = 1'b0;
 		  LRUWriteEn = 1'b1;
-		  if(StallF) begin
+		  if(CPUBusy) begin
 			NextState = STATE_CPU_BUSY;
 			SelAdr = 2'b01;
 		  end else begin
@@ -169,7 +165,7 @@ module icachefsm
           SelAdr = 2'b01;
           NextState = STATE_MISS_SPILL_FETCH_WDV;
         end else begin
-		  if(StallF) begin
+		  if(CPUBusy) begin
 			NextState = STATE_CPU_BUSY;
 			SelAdr = 2'b01;
 		  end else begin
@@ -214,7 +210,7 @@ module icachefsm
         ICacheStallF = 1'b0;
 		LRUWriteEn = 1'b1;
 		
-		if(StallF) begin
+		if(CPUBusy) begin
 		  NextState = STATE_CPU_BUSY_SPILL;
 		  SelAdr = 2'b10;
 		end else begin
@@ -248,7 +244,7 @@ module icachefsm
         ICacheReadEn = 1'b1;
 		ICacheStallF = 1'b0;
 		LRUWriteEn = 1'b1;
-		if(StallF) begin
+		if(CPUBusy) begin
 		  SelAdr = 2'b01;
 		  NextState = STATE_CPU_BUSY;
 		  SelAdr = 2'b01;
@@ -293,7 +289,7 @@ module icachefsm
           SelAdr = 2'b00;
           ICacheStallF = 1'b0;
 		  LRUWriteEn = 1'b1;
-		  if(StallF) begin
+		  if(CPUBusy) begin
 			NextState = STATE_CPU_BUSY_SPILL;
 			SelAdr = 2'b10;
 		  end else begin
@@ -326,7 +322,7 @@ module icachefsm
         SelAdr = 2'b00;
         ICacheStallF = 1'b0;	
 		LRUWriteEn = 1'b1;
-		if(StallF) begin
+		if(CPUBusy) begin
 		  NextState = STATE_CPU_BUSY_SPILL;
 		  SelAdr = 2'b10;
 		end else begin
@@ -335,7 +331,7 @@ module icachefsm
       end
       STATE_CPU_BUSY: begin
 		ICacheStallF = 1'b0;
-        if(StallF) begin
+        if(CPUBusy) begin
 		  NextState = STATE_CPU_BUSY;
 		  SelAdr = 2'b01;
 		end
@@ -346,7 +342,7 @@ module icachefsm
       STATE_CPU_BUSY_SPILL: begin
 		ICacheStallF = 1'b0;
 		ICacheReadEn = 1'b1;
-		if(StallF) begin
+		if(CPUBusy) begin
 		  NextState = STATE_CPU_BUSY_SPILL;
 		  SelAdr = 2'b10;
 		end

wally-pipelined/src/ifu/ifu.sv

@@ -104,6 +104,8 @@ module ifu (
   logic [`XLEN+1:0]            PCFExt;
   logic [`XLEN-1:0] 		   PCBPWrongInvalidate;
   logic 					   BPPredWrongM;
+  logic 					   CacheableF;
+  
   
 
   generate
@@ -136,7 +138,7 @@ module ifu (
        .LoadAccessFaultM(),
        .StoreAccessFaultM(),
        .DisableTranslation(1'b0),
-       .Cacheable(), .Idempotent(), .AtomicAllowed(),
+       .Cacheable(CacheableF), .Idempotent(), .AtomicAllowed(),
 
        .clk, .reset,
        .SATP_REGW,
@@ -165,9 +167,9 @@ module ifu (
   // 1. ram // controlled by `MEM_IROM
   // 2. cache // `MEM_ICACHE
   // 3. wire pass-through
-  icache icache(.clk, .reset, .StallF, .ExceptionM, .PendingInterruptM, .InstrInF, .InstrAckF,
+  icache icache(.clk, .reset, .CPUBusy(StallF), .ExceptionM, .PendingInterruptM, .InstrInF, .InstrAckF,
   .InstrPAdrF, .InstrReadF, .CompressedF, .ICacheStallF, .ITLBMissF, .ITLBWriteF, .FinalInstrRawF,
-
+				.CacheableF,
   .PCNextF(PCNextFPhys),
   .PCPF(PCPFmmu),
   .PCF,