From d4fc3245b0e4d4421d65c6f04a94a91853bd4dad Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 15 Oct 2024 10:11:12 -0500 Subject: [PATCH] Removed ahbsdc submodule since it is no longer used. Updated old submodules pointing to ross144 to rosethompson repos. --- .gitmodules | 7 ++----- addins/ahbsdc | 1 - fpga/generator/wally.tcl | 2 +- 3 files changed, 3 insertions(+), 7 deletions(-) delete mode 160000 addins/ahbsdc diff --git a/.gitmodules b/.gitmodules index b066104f7..eed0bb58f 100644 --- a/.gitmodules +++ b/.gitmodules @@ -20,14 +20,11 @@ branch = dev [submodule "addins/branch-predictor-simulator"] path = addins/branch-predictor-simulator - url = https://github.com/ross144/branch-predictor-simulator -[submodule "addins/ahbsdc"] - path = addins/ahbsdc - url = https://github.com/JacobPease/ahbsdc.git + url = https://github.com/rosethompson/branch-predictor-simulator [submodule "addins/verilog-ethernet"] sparseCheckout = true path = addins/verilog-ethernet - url = https://github.com/ross144/verilog-ethernet.git + url = https://github.com/rosethompson/verilog-ethernet.git [submodule "cvw-arch-verif"] path = addins/cvw-arch-verif url = https://github.com/openhwgroup/cvw-arch-verif diff --git a/addins/ahbsdc b/addins/ahbsdc deleted file mode 160000 index 33418c8dc..000000000 --- a/addins/ahbsdc +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 33418c8dc11baf63e843b0d35f57d22c1e3182e3 diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 5151b0e77..3ca0c3360 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -47,7 +47,7 @@ if {$board=="ArtyA7"} { # read in all other rtl add_files [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv] -set_property include_dirs {../src/CopiedFiles_do_not_add_to_repo/config ../../config/shared ../../addins/ahbsdc/sdc} [current_fileset] +set_property include_dirs {../src/CopiedFiles_do_not_add_to_repo/config ../../config/shared} [current_fileset] # define top level