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Moved simulator into bin, added pLRU clearing

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This commit is contained in:
Limnanthes Serafini 2023-04-03 14:10:27 -07:00
parent 91fe85486c
commit d48a6c1190
1 changed files with 18 additions and 8 deletions
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22
addins/cache-sim/src/CacheSim.py → bin/CacheSim.py Normal file → Executable file
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@ -43,7 +43,7 @@ class Cache:
self.ways[i].append(CacheLine()) self.ways[i].append(CacheLine())
self.pLRU = [] self.pLRU = []
for i in range(numsets): for i in range(self.numsets):
self.pLRU.append([0]*(self.numways-1)) self.pLRU.append([0]*(self.numways-1))
def flush(self): def flush(self):
@ -56,6 +56,11 @@ class Cache:
for line in way: for line in way:
line.valid = False line.valid = False
def clear_pLRU(self):
self.pLRU = []
for i in range(self.numsets):
self.pLRU.append([0]*(self.numways-1))
def splitaddr(self, addr): def splitaddr(self, addr):
# no need for offset in the sim # no need for offset in the sim
setnum = (addr >> self.offsetlen) - ((addr >> (self.setlen + self.offsetlen)) << self.setlen) setnum = (addr >> self.offsetlen) - ((addr >> (self.setlen + self.offsetlen)) << self.setlen)
@ -126,8 +131,10 @@ class Cache:
bottomrow = (self.numways - 1) // 2 #first index on the bottom row of the tree bottomrow = (self.numways - 1) // 2 #first index on the bottom row of the tree
while index < bottomrow: while index < bottomrow:
if tree[index] == 0: if tree[index] == 0:
# Go to the left child
index = index*2 + 1 index = index*2 + 1
else: else: #tree[index] == 1
# Go to the right child
index = index*2 + 2 index = index*2 + 2
victim = (index - bottomrow)*2 victim = (index - bottomrow)*2
@ -161,16 +168,17 @@ if __name__ == "__main__":
cache = Cache(args.numlines, args.numways, args.addrlen, args.taglen) cache = Cache(args.numlines, args.numways, args.addrlen, args.taglen)
# go looking in the sim directory for the file if it doesn't exist # go looking in the sim directory for the file if it doesn't exist
if not os.path.isfile(args.file): # if not os.path.isfile(args.file):
args.file = os.path.expanduser("~/cvw/sim/" + args.file) # args.file = os.path.expanduser("~/cvw/sim/" + args.file)
with open(args.file, "r") as f: with open(args.file, "r") as f:
for ln in f: for ln in f:
ln = ln.strip() ln = ln.strip()
lninfo = ln.split() lninfo = ln.split()
if len(lninfo) < 3: #non-address line if len(lninfo) < 3: #non-address line
if lninfo[0] == 'END': if lninfo[0] == 'BEGIN':
cache.invalidate() # a new test is starting, so 'empty' the cache cache.invalidate() # a new test is starting, so 'empty' the cache
cache.clear_pLRU()
else: else:
if lninfo[1] == 'F': if lninfo[1] == 'F':
cache.flush() cache.flush()
@ -178,11 +186,13 @@ if __name__ == "__main__":
addr = int(lninfo[0], 16) addr = int(lninfo[0], 16)
result = cache.cacheaccess(addr, lninfo[1] == 'W') # add support for A result = cache.cacheaccess(addr, lninfo[1] == 'W') # add support for A
#tag, setnum = cache.splitaddr(addr) #tag, setnum = cache.splitaddr(addr)
#print(tag, setnum, lninfo[2], result) #print(hex(tag), hex(setnum), lninfo[2], result)
if not result == lninfo[2]: if not result == lninfo[2]:
print("Result mismatch at address", lninfo[0], ". Wally:", lninfo[2],", Sim:", result) print("Result mismatch at address", lninfo[0], ". Wally:", lninfo[2],", Sim:", result)
#print() #print()
#print(cache)