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Removed WAdr from cacheway as it is redundant.

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This commit is contained in:
Ross Thompson 2021-12-29 21:39:43 -06:00
parent 7765178a04
commit d474caf24f
3 changed files with 29 additions and 58 deletions
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39
wally-pipelined/src/cache/cacheway.sv vendored
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@ -31,7 +31,6 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
input logic reset, input logic reset,
input logic [$clog2(NUMLINES)-1:0] RAdr, input logic [$clog2(NUMLINES)-1:0] RAdr,
input logic [$clog2(NUMLINES)-1:0] WAdr,
input logic [`PA_BITS-1:0] PAdr, input logic [`PA_BITS-1:0] PAdr,
input logic WriteEnable, input logic WriteEnable,
input logic VDWriteEnable, input logic VDWriteEnable,
@ -64,7 +63,7 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
logic [TAGLEN-1:0] VicDirtyWay; logic [TAGLEN-1:0] VicDirtyWay;
logic [TAGLEN-1:0] FlushThisWay; logic [TAGLEN-1:0] FlushThisWay;
logic [$clog2(NUMLINES)-1:0] RAdrD, WAdrD; logic [$clog2(NUMLINES)-1:0] RAdrD;
logic SetValidD, ClearValidD; logic SetValidD, ClearValidD;
logic SetDirtyD, ClearDirtyD; logic SetDirtyD, ClearDirtyD;
logic WriteEnableD, VDWriteEnableD; logic WriteEnableD, VDWriteEnableD;
@ -76,23 +75,20 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
generate generate
for(words = 0; words < BLOCKLEN/`XLEN; words++) begin : word for(words = 0; words < BLOCKLEN/`XLEN; words++) begin : word
sram1rw #(.DEPTH(`XLEN), sram1rw #(.DEPTH(`XLEN), .WIDTH(NUMLINES))
.WIDTH(NUMLINES)) CacheDataMem(.clk(clk), .Addr(RAdr),
CacheDataMem(.clk(clk), .ReadData(ReadDataBlockWay[(words+1)*`XLEN-1:words*`XLEN] ),
.Addr(RAdr), .WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]),
.ReadData(ReadDataBlockWay[(words+1)*`XLEN-1:words*`XLEN] ), .WriteEnable(WriteEnable & WriteWordEnable[words]));
.WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]),
.WriteEnable(WriteEnable & WriteWordEnable[words]));
end end
endgenerate endgenerate
sram1rw #(.DEPTH(TAGLEN), sram1rw #(.DEPTH(TAGLEN), .WIDTH(NUMLINES))
.WIDTH(NUMLINES))
CacheTagMem(.clk(clk), CacheTagMem(.clk(clk),
.Addr(RAdr), .Addr(RAdr),
.ReadData(ReadTag), .ReadData(ReadTag),
.WriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]),
.WriteEnable(TagWriteEnable)); .WriteEnable(TagWriteEnable));
assign WayHit = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]); assign WayHit = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]);
assign SelectedWay = SelFlush ? FlushWay : assign SelectedWay = SelFlush ? FlushWay :
@ -101,10 +97,6 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
assign VictimDirtyWay = SelFlush ? FlushWay & Dirty & Valid : assign VictimDirtyWay = SelFlush ? FlushWay & Dirty & Valid :
VictimWay & Dirty & Valid; VictimWay & Dirty & Valid;
/* -----\/----- EXCLUDED -----\/-----
assign VictimTagWay = SelFlush & FlushWay ? ReadTag :
VictimWay ? ReadTag : '0;
-----/\----- EXCLUDED -----/\----- */
assign VicDirtyWay = VictimWay ? ReadTag : '0; assign VicDirtyWay = VictimWay ? ReadTag : '0;
assign FlushThisWay = FlushWay ? ReadTag : '0; assign FlushThisWay = FlushWay ? ReadTag : '0;
@ -116,13 +108,12 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
ValidBits <= {NUMLINES{1'b0}}; ValidBits <= {NUMLINES{1'b0}};
else if (InvalidateAll) else if (InvalidateAll)
ValidBits <= {NUMLINES{1'b0}}; ValidBits <= {NUMLINES{1'b0}};
else if (SetValidD & (WriteEnableD | VDWriteEnableD)) ValidBits[WAdrD] <= 1'b1; else if (SetValidD & (WriteEnableD | VDWriteEnableD)) ValidBits[RAdrD] <= 1'b1;
else if (ClearValidD & (WriteEnableD | VDWriteEnableD)) ValidBits[WAdrD] <= 1'b0; else if (ClearValidD & (WriteEnableD | VDWriteEnableD)) ValidBits[RAdrD] <= 1'b0;
end end
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
RAdrD <= RAdr; RAdrD <= RAdr;
WAdrD <= WAdr;
SetValidD <= SetValid; SetValidD <= SetValid;
ClearValidD <= ClearValid; ClearValidD <= ClearValid;
WriteEnableD <= WriteEnable; WriteEnableD <= WriteEnable;
@ -137,8 +128,8 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if (reset) if (reset)
DirtyBits <= {NUMLINES{1'b0}}; DirtyBits <= {NUMLINES{1'b0}};
else if (SetDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[WAdrD] <= 1'b1; else if (SetDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[RAdrD] <= 1'b1;
else if (ClearDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[WAdrD] <= 1'b0; else if (ClearDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[RAdrD] <= 1'b0;
end end
always_ff @(posedge clk) begin always_ff @(posedge clk) begin

22
wally-pipelined/src/cache/dcache.sv vendored
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@ -126,29 +126,19 @@ module dcache
.s(SelAdrM), .s(SelAdrM),
.y(RAdr)); .y(RAdr));
cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN), .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN)) cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN),
MemWay[NUMWAYS-1:0](.clk, .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN))
.reset, MemWay[NUMWAYS-1:0](.clk, .reset, .RAdr,
.RAdr,
.WAdr(RAdr), // *** Reduce after addressing in icache also
.PAdr(LsuPAdrM), .PAdr(LsuPAdrM),
.WriteEnable(SRAMWayWriteEnable), .WriteEnable(SRAMWayWriteEnable),
.VDWriteEnable(VDWriteEnableWay), .VDWriteEnable(VDWriteEnableWay),
.WriteWordEnable(SRAMWordEnable), .WriteWordEnable(SRAMWordEnable),
.TagWriteEnable(SRAMBlockWayWriteEnableM), .TagWriteEnable(SRAMBlockWayWriteEnableM),
.WriteData(SRAMWriteData), .WriteData(SRAMWriteData),
.SetValid, .SetValid, .ClearValid, .SetDirty, .ClearDirty, .SelEvict,
.ClearValid, .VictimWay, .FlushWay, .SelFlush,
.SetDirty,
.ClearDirty,
.SelEvict,
.VictimWay,
.FlushWay,
.SelFlush,
.ReadDataBlockWayMasked(ReadDataBlockWayMaskedM), .ReadDataBlockWayMasked(ReadDataBlockWayMaskedM),
.WayHit, .WayHit, .VictimDirtyWay, .VictimTagWay,
.VictimDirtyWay,
.VictimTagWay,
.InvalidateAll(1'b0)); .InvalidateAll(1'b0));
generate generate

26
wally-pipelined/src/cache/icache.sv vendored
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@ -132,12 +132,9 @@ module icache
cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN), .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN), cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN),
.DIRTY_BITS(0)) .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN), .DIRTY_BITS(0))
MemWay[NUMWAYS-1:0](.clk, MemWay[NUMWAYS-1:0](.clk, .reset, .RAdr,
.reset,
.RAdr(RAdr),
.WAdr(PCTagF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
.PAdr(PCTagF), .PAdr(PCTagF),
.WriteEnable(SRAMWayWriteEnable), .WriteEnable(SRAMWayWriteEnable),
.VDWriteEnable(1'b0), .VDWriteEnable(1'b0),
@ -145,19 +142,12 @@ module icache
.TagWriteEnable(SRAMWayWriteEnable), .TagWriteEnable(SRAMWayWriteEnable),
.WriteData(ICacheMemWriteData), .WriteData(ICacheMemWriteData),
.SetValid(ICacheMemWriteEnable), .SetValid(ICacheMemWriteEnable),
.ClearValid(1'b0), .ClearValid(1'b0), .SetDirty(1'b0), .ClearDirty(1'b0), .SelEvict(1'b0),
.SetDirty(1'b0),
.ClearDirty(1'b0),
.SelEvict(1'b0),
.VictimWay, .VictimWay,
.FlushWay(1'b0), .FlushWay(1'b0), .SelFlush(1'b0),
.SelFlush(1'b0), .ReadDataBlockWayMasked, .WayHit,
.ReadDataBlockWayMasked, .VictimDirtyWay(), .VictimTagWay(),
.WayHit, .InvalidateAll(InvalidateICacheM));
.VictimDirtyWay(),
.VictimTagWay(),
.InvalidateAll(InvalidateICacheM)
);
generate generate
if(NUMWAYS > 1) begin if(NUMWAYS > 1) begin