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change testbench-linux to by default use attempted instruction count for warning/error messages

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bbracker 2022-04-12 21:22:08 -07:00
parent f995ec2a54
commit d3e9703c19
1 changed files with 10 additions and 10 deletions
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20
pipelined/testbench/testbench-linux.sv
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@ -558,14 +558,14 @@ module testbench;
// ========== VALUE-CHECKING MACROS ========== // ========== VALUE-CHECKING MACROS ==========
`define checkEQ(NAME, VAL, EXPECTED) \ `define checkEQ(NAME, VAL, EXPECTED) \
if(VAL != EXPECTED) begin \ if(VAL != EXPECTED) begin \
$display("%tns, %d instrs: %s %x differs from expected %x", $time, InstrCountW, NAME, VAL, EXPECTED); \ $display("%tns, %d instrs: %s %x differs from expected %x", $time, AttemptedInstructionCount, NAME, VAL, EXPECTED); \
if ((NAME == "PCW") | (`DEBUG_TRACE >= 2)) fault = 1; \ if ((NAME == "PCW") | (`DEBUG_TRACE >= 2)) fault = 1; \
end end
`define checkCSR(CSR) \ `define checkCSR(CSR) \
begin \ begin \
if (CSR != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin \ if (CSR != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin \
$display("%tns, %d instrs: CSR %s = %016x, does not equal expected value %016x", $time, InstrCountW, ExpectedCSRArrayW[NumCSRPostWIndex], CSR, ExpectedCSRArrayValueW[NumCSRPostWIndex]); \ $display("%tns, %d instrs: CSR %s = %016x, does not equal expected value %016x", $time, AttemptedInstructionCount, ExpectedCSRArrayW[NumCSRPostWIndex], CSR, ExpectedCSRArrayValueW[NumCSRPostWIndex]); \
if(`DEBUG_TRACE >= 3) fault = 1; \ if(`DEBUG_TRACE >= 3) fault = 1; \
end \ end \
end end
@ -625,12 +625,12 @@ module testbench;
// override on special conditions // override on special conditions
if(~dut.core.StallW) begin if(~dut.core.StallW) begin
if(textW.substr(0,5) == "rdtime") begin if(textW.substr(0,5) == "rdtime") begin
//$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, InstrCountW); //$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, AttemptedInstructionCount);
if(!NO_IE_MTIME_CHECKPOINT) if(!NO_IE_MTIME_CHECKPOINT)
release dut.uncore.clint.clint.MTIME; release dut.uncore.clint.clint.MTIME;
end end
//if (ExpectedIEUAdrM == 'h10000005) begin //if (ExpectedIEUAdrM == 'h10000005) begin
//$display("%tns, %d instrs: releasing force of ReadDataM.", $time, InstrCountW); //$display("%tns, %d instrs: releasing force of ReadDataM.", $time, AttemptedInstructionCount);
//release dut.core.ieu.dp.ReadDataM; //release dut.core.ieu.dp.ReadDataM;
//end //end
end end
@ -644,11 +644,11 @@ module testbench;
if (checkInstrW) begin if (checkInstrW) begin
InstrCountW += 1; InstrCountW += 1;
// print progress message // print progress message
if (InstrCountW % 'd100000 == 0) $display("Reached %d instructions", InstrCountW); if (AttemptedInstructionCount % 'd100000 == 0) $display("Reached %d instructions", AttemptedInstructionCount);
// turn on waves // turn on waves
if (InstrCountW == INSTR_WAVEON) $stop; if (AttemptedInstructionCount == INSTR_WAVEON) $stop;
// end sim // end sim
if ((InstrCountW == INSTR_LIMIT) & (INSTR_LIMIT!=0)) $stop; if ((AttemptedInstructionCount == INSTR_LIMIT) & (INSTR_LIMIT!=0)) $stop;
fault = 0; fault = 0;
if (`DEBUG_TRACE >= 1) begin if (`DEBUG_TRACE >= 1) begin
`checkEQ("PCW",PCW,ExpectedPCW) `checkEQ("PCW",PCW,ExpectedPCW)
@ -657,8 +657,8 @@ module testbench;
`checkEQ("Instr Count",dut.core.priv.priv.csr.counters.counters.INSTRET_REGW,InstrCountW) `checkEQ("Instr Count",dut.core.priv.priv.csr.counters.counters.INSTRET_REGW,InstrCountW)
#2; // delay 2 ns. #2; // delay 2 ns.
if(`DEBUG_TRACE >= 5) begin if(`DEBUG_TRACE >= 5) begin
$display("%tns, %d instrs: Reg Write Address %02d ? expected value: %02d", $time, InstrCountW, dut.core.ieu.dp.regf.a3, ExpectedRegAdrW); $display("%tns, %d instrs: Reg Write Address %02d ? expected value: %02d", $time, AttemptedInstructionCount, dut.core.ieu.dp.regf.a3, ExpectedRegAdrW);
$display("%tns, %d instrs: RF[%02d] %016x ? expected value: %016x", $time, InstrCountW, ExpectedRegAdrW, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW); $display("%tns, %d instrs: RF[%02d] %016x ? expected value: %016x", $time, AttemptedInstructionCount, ExpectedRegAdrW, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW);
end end
if (RegWriteW == "GPR") begin if (RegWriteW == "GPR") begin
`checkEQ("Reg Write Address",dut.core.ieu.dp.regf.a3,ExpectedRegAdrW) `checkEQ("Reg Write Address",dut.core.ieu.dp.regf.a3,ExpectedRegAdrW)
@ -709,7 +709,7 @@ module testbench;
end end
if (fault == 1) begin if (fault == 1) begin
errorCount +=1; errorCount +=1;
$display("processed %0d instructions with %0d warnings", InstrCountW, warningCount); $display("processed %0d instructions with %0d warnings", AttemptedInstructionCount, warningCount);
$stop; $stop;
end end
end // if (`DEBUG_TRACE >= 1) end // if (`DEBUG_TRACE >= 1)