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Fix derived configs with D_SUPPORTED = 0

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Jordan Carlin 2024-06-26 21:24:34 -07:00
parent 1a1da9b2c4
commit d3bb39d918
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1 changed files with 33 additions and 2 deletions
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35
config/derivlist.txt
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@ -106,6 +106,7 @@ F_SUPPORTED 0
ZCF_SUPPORTED 0 ZCF_SUPPORTED 0
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0 ZCD_SUPPORTED 0
deriv syn_sram_rv64gc_noFPU syn_sram_rv64gc_noPriv deriv syn_sram_rv64gc_noFPU syn_sram_rv64gc_noPriv
F_SUPPORTED 0 F_SUPPORTED 0
ZCF_SUPPORTED 0 ZCF_SUPPORTED 0
@ -395,22 +396,24 @@ VIRTMEM_SUPPORTED 0
deriv nodcache_rv32gc rv32gc deriv nodcache_rv32gc rv32gc
DCACHE_SUPPORTED 0 DCACHE_SUPPORTED 0
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0
ZALRSC_SUPPORTED 0 ZALRSC_SUPPORTED 0
ZAAMO_SUPPORTED 0 ZAAMO_SUPPORTED 0
ZICBOM_SUPPORTED 0 ZICBOM_SUPPORTED 0
ZICBOZ_SUPPORTED 0 ZICBOZ_SUPPORTED 0
VIRTMEM_SUPPORTED 0 VIRTMEM_SUPPORTED 0
# nocache_rv32gc must also disable several features incompatible with no cache # nocache_rv32gc must also disable several features incompatible with no cache
deriv nocache_rv32gc rv32gc deriv nocache_rv32gc rv32gc
ICACHE_SUPPORTED 0 ICACHE_SUPPORTED 0
DCACHE_SUPPORTED 0 DCACHE_SUPPORTED 0
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0
ZALRSC_SUPPORTED 0 ZALRSC_SUPPORTED 0
ZAAMO_SUPPORTED 0 ZAAMO_SUPPORTED 0
ZICBOM_SUPPORTED 0 ZICBOM_SUPPORTED 0
ZICBOZ_SUPPORTED 0 ZICBOZ_SUPPORTED 0
VIRTMEM_SUPPORTED 0 VIRTMEM_SUPPORTED 0
deriv noicache_rv64gc rv64gc deriv noicache_rv64gc rv64gc
ICACHE_SUPPORTED 0 ICACHE_SUPPORTED 0
@ -787,10 +790,12 @@ ZKNH_SUPPORTED 1
deriv f_rv32gc rv32gc deriv f_rv32gc rv32gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0
ZFH_SUPPORTED 0 ZFH_SUPPORTED 0
deriv fh_rv32gc rv32gc deriv fh_rv32gc rv32gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0
ZFH_SUPPORTED 1 ZFH_SUPPORTED 1
deriv fd_rv32gc rv32gc deriv fd_rv32gc rv32gc
@ -809,10 +814,12 @@ ZFH_SUPPORTED 1
deriv f_rv64gc rv64gc deriv f_rv64gc rv64gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0
ZFH_SUPPORTED 0 ZFH_SUPPORTED 0
deriv fh_rv64gc rv64gc deriv fh_rv64gc rv64gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0
ZFH_SUPPORTED 1 ZFH_SUPPORTED 1
deriv fd_rv64gc rv64gc deriv fd_rv64gc rv64gc
@ -872,100 +879,124 @@ IEEE754 1
#### F_only, RK variable #### F_only, RK variable
deriv f_div_2_1_rv32gc div_2_1_rv32gc deriv f_div_2_1_rv32gc div_2_1_rv32gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0
ZFH_SUPPORTED 0 ZFH_SUPPORTED 0
deriv f_div_2_2_rv32gc div_2_2_rv32gc deriv f_div_2_2_rv32gc div_2_2_rv32gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0
ZFH_SUPPORTED 0 ZFH_SUPPORTED 0
deriv f_div_2_4_rv32gc div_2_4_rv32gc deriv f_div_2_4_rv32gc div_2_4_rv32gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0
ZFH_SUPPORTED 0 ZFH_SUPPORTED 0
deriv f_div_4_1_rv32gc div_4_1_rv32gc deriv f_div_4_1_rv32gc div_4_1_rv32gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0
ZFH_SUPPORTED 0 ZFH_SUPPORTED 0
deriv f_div_4_2_rv32gc div_4_2_rv32gc deriv f_div_4_2_rv32gc div_4_2_rv32gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0
ZFH_SUPPORTED 0 ZFH_SUPPORTED 0
deriv f_div_4_4_rv32gc div_4_4_rv32gc deriv f_div_4_4_rv32gc div_4_4_rv32gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0
ZFH_SUPPORTED 0 ZFH_SUPPORTED 0
deriv f_div_2_1_rv64gc div_2_1_rv64gc deriv f_div_2_1_rv64gc div_2_1_rv64gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0
ZFH_SUPPORTED 0 ZFH_SUPPORTED 0
deriv f_div_2_2_rv64gc div_2_2_rv64gc deriv f_div_2_2_rv64gc div_2_2_rv64gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0
ZFH_SUPPORTED 0 ZFH_SUPPORTED 0
deriv f_div_2_4_rv64gc div_2_4_rv64gc deriv f_div_2_4_rv64gc div_2_4_rv64gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0
ZFH_SUPPORTED 0 ZFH_SUPPORTED 0
deriv f_div_4_1_rv64gc div_4_1_rv64gc deriv f_div_4_1_rv64gc div_4_1_rv64gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0
ZFH_SUPPORTED 0 ZFH_SUPPORTED 0
deriv f_div_4_2_rv64gc div_4_2_rv64gc deriv f_div_4_2_rv64gc div_4_2_rv64gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0
ZFH_SUPPORTED 0 ZFH_SUPPORTED 0
deriv f_div_4_4_rv64gc div_4_4_rv64gc deriv f_div_4_4_rv64gc div_4_4_rv64gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0
ZFH_SUPPORTED 0 ZFH_SUPPORTED 0
#### FH_only, RK variable #### FH_only, RK variable
deriv fh_div_2_1_rv32gc div_2_1_rv32gc deriv fh_div_2_1_rv32gc div_2_1_rv32gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0
ZFH_SUPPORTED 1 ZFH_SUPPORTED 1
deriv fh_div_2_2_rv32gc div_2_2_rv32gc deriv fh_div_2_2_rv32gc div_2_2_rv32gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0
ZFH_SUPPORTED 1 ZFH_SUPPORTED 1
deriv fh_div_2_4_rv32gc div_2_4_rv32gc deriv fh_div_2_4_rv32gc div_2_4_rv32gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0
ZFH_SUPPORTED 1 ZFH_SUPPORTED 1
deriv fh_div_4_1_rv32gc div_4_1_rv32gc deriv fh_div_4_1_rv32gc div_4_1_rv32gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0
ZFH_SUPPORTED 1 ZFH_SUPPORTED 1
deriv fh_div_4_2_rv32gc div_4_2_rv32gc deriv fh_div_4_2_rv32gc div_4_2_rv32gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0
ZFH_SUPPORTED 1 ZFH_SUPPORTED 1
deriv fh_div_4_4_rv32gc div_4_4_rv32gc deriv fh_div_4_4_rv32gc div_4_4_rv32gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0
ZFH_SUPPORTED 1 ZFH_SUPPORTED 1
deriv fh_div_2_1_rv64gc div_2_1_rv64gc deriv fh_div_2_1_rv64gc div_2_1_rv64gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0
ZFH_SUPPORTED 1 ZFH_SUPPORTED 1
deriv fh_div_2_2_rv64gc div_2_2_rv64gc deriv fh_div_2_2_rv64gc div_2_2_rv64gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0
ZFH_SUPPORTED 1 ZFH_SUPPORTED 1
deriv fh_div_2_4_rv64gc div_2_4_rv64gc deriv fh_div_2_4_rv64gc div_2_4_rv64gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0
ZFH_SUPPORTED 1 ZFH_SUPPORTED 1
deriv fh_div_4_1_rv64gc div_4_1_rv64gc deriv fh_div_4_1_rv64gc div_4_1_rv64gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0
ZFH_SUPPORTED 1 ZFH_SUPPORTED 1
deriv fh_div_4_2_rv64gc div_4_2_rv64gc deriv fh_div_4_2_rv64gc div_4_2_rv64gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0
ZFH_SUPPORTED 1 ZFH_SUPPORTED 1
deriv fh_div_4_4_rv64gc div_4_4_rv64gc deriv fh_div_4_4_rv64gc div_4_4_rv64gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0
ZFH_SUPPORTED 1 ZFH_SUPPORTED 1
# FD only , rk variable # FD only , rk variable