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https://github.com/openhwgroup/cvw
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Subwordread now parameterized.
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@ -27,8 +27,6 @@
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// and limitations under the License.
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module dtim import cvw::*; #(parameter cvw_t P) (
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module dtim import cvw::*; #(parameter cvw_t P) (
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input logic clk,
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input logic clk,
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input logic FlushW,
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input logic FlushW,
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@ -27,8 +27,6 @@
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// and limitations under the License.
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module endianswap #(parameter LEN) (
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module endianswap #(parameter LEN) (
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input logic BigEndianM,
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input logic BigEndianM,
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input logic [LEN-1:0] a,
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input logic [LEN-1:0] a,
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@ -335,7 +335,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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/////////////////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Subword Accesses
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// Subword Accesses
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/////////////////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////////////////
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subwordread subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
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subwordread #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
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.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
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.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
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subwordwrite subwordwrite(.LSUFunct3M, .IMAFWriteDataM, .LittleEndianWriteDataM);
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subwordwrite subwordwrite(.LSUFunct3M, .IMAFWriteDataM, .LittleEndianWriteDataM);
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@ -29,14 +29,14 @@
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`include "wally-config.vh"
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`include "wally-config.vh"
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module subwordread
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module subwordread #(parameter LLEN)
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(
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(
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input logic [`LLEN-1:0] ReadDataWordMuxM,
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input logic [LLEN-1:0] ReadDataWordMuxM,
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input logic [2:0] PAdrM,
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input logic [2:0] PAdrM,
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input logic [2:0] Funct3M,
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input logic [2:0] Funct3M,
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input logic FpLoadStoreM,
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input logic FpLoadStoreM,
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input logic BigEndianM,
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input logic BigEndianM,
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output logic [`LLEN-1:0] ReadDataM
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output logic [LLEN-1:0] ReadDataM
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);
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);
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logic [7:0] ByteM;
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logic [7:0] ByteM;
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@ -46,7 +46,7 @@ module subwordread
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// Funct3M[1:0] is the size of the memory access.
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// Funct3M[1:0] is the size of the memory access.
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assign PAdrSwap = PAdrM ^ {3{BigEndianM}};
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assign PAdrSwap = PAdrM ^ {3{BigEndianM}};
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if (`LLEN == 64) begin:swrmux
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if (LLEN == 64) begin:swrmux
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// ByteMe mux
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// ByteMe mux
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always_comb
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always_comb
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case(PAdrSwap[2:0])
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case(PAdrSwap[2:0])
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@ -83,14 +83,14 @@ module subwordread
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// sign extension/ NaN boxing
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// sign extension/ NaN boxing
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always_comb
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always_comb
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case(Funct3M)
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case(Funct3M)
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3'b000: ReadDataM = {{`LLEN-8{ByteM[7]}}, ByteM}; // lb
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3'b000: ReadDataM = {{LLEN-8{ByteM[7]}}, ByteM}; // lb
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3'b001: ReadDataM = {{`LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh
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3'b001: ReadDataM = {{LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh
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3'b010: ReadDataM = {{`LLEN-32{WordM[31]|FpLoadStoreM}}, WordM[31:0]}; // lw/flw
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3'b010: ReadDataM = {{LLEN-32{WordM[31]|FpLoadStoreM}}, WordM[31:0]}; // lw/flw
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3'b011: ReadDataM = {{`LLEN-64{DblWordM[63]|FpLoadStoreM}}, DblWordM[63:0]}; // ld/fld
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3'b011: ReadDataM = {{LLEN-64{DblWordM[63]|FpLoadStoreM}}, DblWordM[63:0]}; // ld/fld
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3'b100: ReadDataM = {{`LLEN-8{1'b0}}, ByteM[7:0]}; // lbu
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3'b100: ReadDataM = {{LLEN-8{1'b0}}, ByteM[7:0]}; // lbu
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//3'b100: ReadDataM = FpLoadStoreM ? ReadDataWordMuxM : {{`LLEN-8{1'b0}}, ByteM[7:0]}; // lbu/flq - only needed when LLEN=128
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//3'b100: ReadDataM = FpLoadStoreM ? ReadDataWordMuxM : {{LLEN-8{1'b0}}, ByteM[7:0]}; // lbu/flq - only needed when LLEN=128
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3'b101: ReadDataM = {{`LLEN-16{1'b0}}, HalfwordM[15:0]}; // lhu
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3'b101: ReadDataM = {{LLEN-16{1'b0}}, HalfwordM[15:0]}; // lhu
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3'b110: ReadDataM = {{`LLEN-32{1'b0}}, WordM[31:0]}; // lwu
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3'b110: ReadDataM = {{LLEN-32{1'b0}}, WordM[31:0]}; // lwu
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default: ReadDataM = ReadDataWordMuxM; // Shouldn't happen
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default: ReadDataM = ReadDataWordMuxM; // Shouldn't happen
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endcase
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endcase
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@ -114,12 +114,12 @@ module subwordread
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// sign extension
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// sign extension
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always_comb
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always_comb
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case(Funct3M)
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case(Funct3M)
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3'b000: ReadDataM = {{`LLEN-8{ByteM[7]}}, ByteM}; // lb
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3'b000: ReadDataM = {{LLEN-8{ByteM[7]}}, ByteM}; // lb
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3'b001: ReadDataM = {{`LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh
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3'b001: ReadDataM = {{LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh
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3'b010: ReadDataM = {{`LLEN-32{ReadDataWordMuxM[31]|FpLoadStoreM}}, ReadDataWordMuxM[31:0]}; // lw/flw
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3'b010: ReadDataM = {{LLEN-32{ReadDataWordMuxM[31]|FpLoadStoreM}}, ReadDataWordMuxM[31:0]}; // lw/flw
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3'b011: ReadDataM = ReadDataWordMuxM; // fld
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3'b011: ReadDataM = ReadDataWordMuxM; // fld
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3'b100: ReadDataM = {{`LLEN-8{1'b0}}, ByteM[7:0]}; // lbu
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3'b100: ReadDataM = {{LLEN-8{1'b0}}, ByteM[7:0]}; // lbu
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3'b101: ReadDataM = {{`LLEN-16{1'b0}}, HalfwordM[15:0]}; // lhu
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3'b101: ReadDataM = {{LLEN-16{1'b0}}, HalfwordM[15:0]}; // lhu
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default: ReadDataM = ReadDataWordMuxM; // Shouldn't happen
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default: ReadDataM = ReadDataWordMuxM; // Shouldn't happen
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endcase
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endcase
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end
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end
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