mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Fixed walker fault interaction with dcache.
This commit is contained in:
Ross Thompson
parent
5ca7dc619c
commit
d3715acf2d
@ -13,19 +13,19 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM
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add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
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add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
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@ -241,81 +241,83 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW
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add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/HPTWTranslate
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add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/CurrState
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add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW
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add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW
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add wave -noupdate -expand -group lsu -group dcache -color Gold /testbench/dut/hart/lsu/dcache/CurrState
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add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/CurrState
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WalkerPageFaultM
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr
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add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM
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add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
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add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM
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add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
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add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM
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add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag
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add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
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add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty
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add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid
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add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM
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add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM
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add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
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add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
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add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
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add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
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add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
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add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
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add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
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add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM
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add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM
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add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
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add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
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add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
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add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
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add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
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add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
|
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW
|
add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
|
||||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
|
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW
|
||||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
|
||||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
|
||||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
|
||||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
|
||||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/SVMode
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -label {Virtual Address} /testbench/dut/hart/lsu/dmmu/Address
|
add wave -noupdate -expand -group lsu -expand -group dtlb -label {Virtual Address} /testbench/dut/hart/lsu/dmmu/Address
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/TLBPageFault
|
add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/TLBPageFault
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/LoadAccessFaultM
|
add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/LoadAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/StoreAccessFaultM
|
add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/StoreAccessFaultM
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBPAdr
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/Address
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBWrite
|
||||||
add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PhysicalAddress
|
add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PhysicalAddress
|
||||||
add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/SelRegions
|
add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/SelRegions
|
||||||
add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/Cacheable
|
add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/Cacheable
|
||||||
@ -325,27 +327,36 @@ add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu
|
|||||||
add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/PMAInstrAccessFaultF
|
add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/PMAInstrAccessFaultF
|
||||||
add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/PMALoadAccessFaultM
|
add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/PMALoadAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/PMAStoreAccessFaultM
|
add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/PMAStoreAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF
|
add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
|
add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
|
add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWTranslate
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/EndWalk
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/EndWalk
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/PreviousWalkerState
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadM
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadPTE
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadPTE
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTableEntryF
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTableEntryM
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -divider data
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTypeF
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTypeM
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/HPTWPAdrE
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/HPTWPAdrM
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/HPTWRead
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -divider data
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF
|
||||||
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HCLK
|
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HCLK
|
||||||
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HSELPLIC
|
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HSELPLIC
|
||||||
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HADDR
|
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HADDR
|
||||||
@ -417,7 +428,7 @@ add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HADDR
|
|||||||
add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWRITE
|
add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWRITE
|
||||||
add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWDATA
|
add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWDATA
|
||||||
TreeUpdate [SetDefaultTree]
|
TreeUpdate [SetDefaultTree]
|
||||||
WaveRestoreCursors {{Cursor 4} {10516 ns} 0}
|
WaveRestoreCursors {{Cursor 4} {29656 ns} 0} {{Cursor 2} {28907 ns} 0} {{Cursor 3} {27874 ns} 0}
|
||||||
quietly wave cursor active 1
|
quietly wave cursor active 1
|
||||||
configure wave -namecolwidth 250
|
configure wave -namecolwidth 250
|
||||||
configure wave -valuecolwidth 297
|
configure wave -valuecolwidth 297
|
||||||
@ -433,4 +444,4 @@ configure wave -griddelta 40
|
|||||||
configure wave -timeline 0
|
configure wave -timeline 0
|
||||||
configure wave -timelineunits ns
|
configure wave -timelineunits ns
|
||||||
update
|
update
|
||||||
WaveRestoreZoom {10473 ns} {10589 ns}
|
WaveRestoreZoom {29565 ns} {29803 ns}
|
||||||
|
|||||||
16
wally-pipelined/src/cache/dcache.sv
vendored
16
wally-pipelined/src/cache/dcache.sv
vendored
@ -53,7 +53,9 @@ module dcache
|
|||||||
input logic DTLBMissM,
|
input logic DTLBMissM,
|
||||||
input logic CacheableM,
|
input logic CacheableM,
|
||||||
input logic DTLBWriteM,
|
input logic DTLBWriteM,
|
||||||
input logic SelPTW,
|
// from ptw
|
||||||
|
input logic SelPTW,
|
||||||
|
input logic WalkerPageFaultM,
|
||||||
// ahb side
|
// ahb side
|
||||||
output logic [`PA_BITS-1:0] AHBPAdr, // to ahb
|
output logic [`PA_BITS-1:0] AHBPAdr, // to ahb
|
||||||
output logic AHBRead,
|
output logic AHBRead,
|
||||||
@ -164,8 +166,8 @@ module dcache
|
|||||||
STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK,
|
STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK,
|
||||||
STATE_PTW_READ_MISS_READ_WORD,
|
STATE_PTW_READ_MISS_READ_WORD,
|
||||||
STATE_PTW_READ_MISS_READ_WORD_DELAY,
|
STATE_PTW_READ_MISS_READ_WORD_DELAY,
|
||||||
STATE_PTW_ACCESS_AFTER_WALK,
|
STATE_PTW_ACCESS_AFTER_WALK,
|
||||||
STATE_PTW_UPDATE_TLB,
|
STATE_PTW_UPDATE_TLB,
|
||||||
|
|
||||||
STATE_UNCACHED_WRITE,
|
STATE_UNCACHED_WRITE,
|
||||||
STATE_UNCACHED_WRITE_DONE,
|
STATE_UNCACHED_WRITE_DONE,
|
||||||
@ -599,7 +601,7 @@ module dcache
|
|||||||
// now all output connect to PTW instead of CPU.
|
// now all output connect to PTW instead of CPU.
|
||||||
CommittedM = 1'b1;
|
CommittedM = 1'b1;
|
||||||
// return to ready if page table walk completed.
|
// return to ready if page table walk completed.
|
||||||
if (~SelPTW) begin
|
if (~SelPTW & ~WalkerPageFaultM) begin
|
||||||
NextState = STATE_PTW_ACCESS_AFTER_WALK;
|
NextState = STATE_PTW_ACCESS_AFTER_WALK;
|
||||||
|
|
||||||
// read hit valid cached
|
// read hit valid cached
|
||||||
@ -614,6 +616,12 @@ module dcache
|
|||||||
CntReset = 1'b1;
|
CntReset = 1'b1;
|
||||||
DCacheStall = 1'b1;
|
DCacheStall = 1'b1;
|
||||||
end
|
end
|
||||||
|
|
||||||
|
// walker has issue abort back to ready
|
||||||
|
else if(~SelPTW & WalkerPageFaultM) begin
|
||||||
|
NextState = STATE_READY;
|
||||||
|
DCacheStall = 1'b0;
|
||||||
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
STATE_PTW_READ_MISS_FETCH_WDV: begin
|
STATE_PTW_READ_MISS_FETCH_WDV: begin
|
||||||
|
|||||||
@ -147,6 +147,7 @@ module lsu
|
|||||||
logic CommittedMfromDCache;
|
logic CommittedMfromDCache;
|
||||||
logic PendingInterruptMtoDCache;
|
logic PendingInterruptMtoDCache;
|
||||||
logic FlushWtoDCache;
|
logic FlushWtoDCache;
|
||||||
|
logic WalkerPageFaultM;
|
||||||
|
|
||||||
|
|
||||||
pagetablewalker pagetablewalker(
|
pagetablewalker pagetablewalker(
|
||||||
@ -169,20 +170,20 @@ module lsu
|
|||||||
.HPTWStall(HPTWStall),
|
.HPTWStall(HPTWStall),
|
||||||
.HPTWPAdrE(HPTWPAdrE),
|
.HPTWPAdrE(HPTWPAdrE),
|
||||||
.HPTWPAdrM(HPTWPAdrM),
|
.HPTWPAdrM(HPTWPAdrM),
|
||||||
.HPTWReadM(HPTWReadM),
|
.HPTWRead(HPTWRead),
|
||||||
.SelPTW(SelPTW),
|
.SelPTW(SelPTW),
|
||||||
.WalkerInstrPageFaultF(WalkerInstrPageFaultF),
|
.WalkerInstrPageFaultF(WalkerInstrPageFaultF),
|
||||||
.WalkerLoadPageFaultM(WalkerLoadPageFaultM),
|
.WalkerLoadPageFaultM(WalkerLoadPageFaultM),
|
||||||
.WalkerStorePageFaultM(WalkerStorePageFaultM));
|
.WalkerStorePageFaultM(WalkerStorePageFaultM));
|
||||||
|
|
||||||
|
assign WalkerPageFaultM = WalkerStorePageFaultM | WalkerLoadPageFaultM;
|
||||||
|
|
||||||
// arbiter between IEU and pagetablewalker
|
// arbiter between IEU and pagetablewalker
|
||||||
lsuArb arbiter(.clk(clk),
|
lsuArb arbiter(.clk(clk),
|
||||||
.reset(reset),
|
.reset(reset),
|
||||||
// HPTW connection
|
// HPTW connection
|
||||||
.SelPTW(SelPTW),
|
.SelPTW(SelPTW),
|
||||||
.HPTWReadM(HPTWReadM),
|
.HPTWRead(HPTWRead),
|
||||||
.HPTWPAdrE(HPTWPAdrE),
|
.HPTWPAdrE(HPTWPAdrE),
|
||||||
.HPTWPAdrM(HPTWPAdrM),
|
.HPTWPAdrM(HPTWPAdrM),
|
||||||
//.HPTWReadPTE(HPTWReadPTE),
|
//.HPTWReadPTE(HPTWReadPTE),
|
||||||
@ -338,6 +339,7 @@ module lsu
|
|||||||
.CacheableM(CacheableMtoDCache),
|
.CacheableM(CacheableMtoDCache),
|
||||||
.DTLBWriteM(DTLBWriteM),
|
.DTLBWriteM(DTLBWriteM),
|
||||||
.SelPTW(SelPTW),
|
.SelPTW(SelPTW),
|
||||||
|
.WalkerPageFaultM(WalkerPageFaultM),
|
||||||
|
|
||||||
// AHB connection
|
// AHB connection
|
||||||
.AHBPAdr(DCtoAHBPAdrM),
|
.AHBPAdr(DCtoAHBPAdrM),
|
||||||
|
|||||||
@ -31,7 +31,7 @@ module lsuArb
|
|||||||
|
|
||||||
// from page table walker
|
// from page table walker
|
||||||
input logic SelPTW,
|
input logic SelPTW,
|
||||||
input logic HPTWReadM,
|
input logic HPTWRead,
|
||||||
input logic [`XLEN-1:0] HPTWPAdrE,
|
input logic [`XLEN-1:0] HPTWPAdrE,
|
||||||
input logic [`XLEN-1:0] HPTWPAdrM,
|
input logic [`XLEN-1:0] HPTWPAdrM,
|
||||||
// to page table walker.
|
// to page table walker.
|
||||||
@ -77,7 +77,7 @@ module lsuArb
|
|||||||
|
|
||||||
// multiplex the outputs to LSU
|
// multiplex the outputs to LSU
|
||||||
assign DisableTranslation = SelPTW; // change names between SelPTW would be confusing in DTLB.
|
assign DisableTranslation = SelPTW; // change names between SelPTW would be confusing in DTLB.
|
||||||
assign MemRWMtoDCache = SelPTW ? {HPTWReadM, 1'b0} : MemRWM;
|
assign MemRWMtoDCache = SelPTW ? {HPTWRead, 1'b0} : MemRWM;
|
||||||
|
|
||||||
generate
|
generate
|
||||||
assign PTWSize = (`XLEN==32 ? 3'b010 : 3'b011); // 32 or 64-bit access from htpw
|
assign PTWSize = (`XLEN==32 ? 3'b010 : 3'b011); // 32 or 64-bit access from htpw
|
||||||
|
|||||||
@ -117,9 +117,10 @@ module mmu #(parameter TLB_ENTRIES = 8, // nuber of TLB Entries
|
|||||||
pmpchecker pmpchecker(.*);
|
pmpchecker pmpchecker(.*);
|
||||||
|
|
||||||
|
|
||||||
|
// If TLB miss and translating we want to not have faults from the PMA and PMP checkers.
|
||||||
assign SquashBusAccess = PMASquashBusAccess | PMPSquashBusAccess;
|
assign SquashBusAccess = PMASquashBusAccess | PMPSquashBusAccess;
|
||||||
assign InstrAccessFaultF = PMAInstrAccessFaultF | PMPInstrAccessFaultF;
|
assign InstrAccessFaultF = (PMAInstrAccessFaultF | PMPInstrAccessFaultF) & ~(Translate & ~TLBHit);
|
||||||
assign LoadAccessFaultM = PMALoadAccessFaultM | PMPLoadAccessFaultM;
|
assign LoadAccessFaultM = (PMALoadAccessFaultM | PMPLoadAccessFaultM) & ~(Translate & ~TLBHit);
|
||||||
assign StoreAccessFaultM = PMAStoreAccessFaultM | PMPStoreAccessFaultM;
|
assign StoreAccessFaultM = (PMAStoreAccessFaultM | PMPStoreAccessFaultM) & ~(Translate & ~TLBHit);
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|||||||
@ -60,7 +60,7 @@ module pagetablewalker
|
|||||||
// *** modify to send to LSU
|
// *** modify to send to LSU
|
||||||
output logic [`XLEN-1:0] HPTWPAdrE, // this probalby should be `PA_BITS wide
|
output logic [`XLEN-1:0] HPTWPAdrE, // this probalby should be `PA_BITS wide
|
||||||
output logic [`XLEN-1:0] HPTWPAdrM, // this probalby should be `PA_BITS wide
|
output logic [`XLEN-1:0] HPTWPAdrM, // this probalby should be `PA_BITS wide
|
||||||
output logic HPTWReadM,
|
output logic HPTWRead,
|
||||||
|
|
||||||
|
|
||||||
// Faults
|
// Faults
|
||||||
@ -69,7 +69,6 @@ module pagetablewalker
|
|||||||
output logic WalkerStorePageFaultM
|
output logic WalkerStorePageFaultM
|
||||||
);
|
);
|
||||||
|
|
||||||
logic HPTWReadE;
|
|
||||||
|
|
||||||
generate
|
generate
|
||||||
if (`MEM_VIRTMEM) begin
|
if (`MEM_VIRTMEM) begin
|
||||||
@ -179,8 +178,10 @@ module pagetablewalker
|
|||||||
if (`XLEN == 32) begin
|
if (`XLEN == 32) begin
|
||||||
logic [9:0] VPN1, VPN0;
|
logic [9:0] VPN1, VPN0;
|
||||||
|
|
||||||
flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
|
flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
|
||||||
|
|
||||||
|
flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState);
|
||||||
|
|
||||||
/* -----\/----- EXCLUDED -----\/-----
|
/* -----\/----- EXCLUDED -----\/-----
|
||||||
assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV) && ~HPTWStall;
|
assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV) && ~HPTWStall;
|
||||||
-----/\----- EXCLUDED -----/\----- */
|
-----/\----- EXCLUDED -----/\----- */
|
||||||
@ -189,7 +190,7 @@ module pagetablewalker
|
|||||||
always_comb begin
|
always_comb begin
|
||||||
PRegEn = 1'b0;
|
PRegEn = 1'b0;
|
||||||
TranslationPAdr = '0;
|
TranslationPAdr = '0;
|
||||||
HPTWReadE = 1'b0;
|
HPTWRead = 1'b0;
|
||||||
PageTableEntry = '0;
|
PageTableEntry = '0;
|
||||||
PageType = '0;
|
PageType = '0;
|
||||||
DTLBWriteM = '0;
|
DTLBWriteM = '0;
|
||||||
@ -218,7 +219,7 @@ module pagetablewalker
|
|||||||
|
|
||||||
LEVEL1_WDV: begin
|
LEVEL1_WDV: begin
|
||||||
TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00};
|
TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00};
|
||||||
HPTWReadE = 1'b1;
|
HPTWRead = 1'b1;
|
||||||
if (HPTWStall) begin
|
if (HPTWStall) begin
|
||||||
NextWalkerState = LEVEL1_WDV;
|
NextWalkerState = LEVEL1_WDV;
|
||||||
end else begin
|
end else begin
|
||||||
@ -240,7 +241,7 @@ module pagetablewalker
|
|||||||
else if (ValidPTE && ~LeafPTE) begin
|
else if (ValidPTE && ~LeafPTE) begin
|
||||||
NextWalkerState = LEVEL0_SET_ADRE;
|
NextWalkerState = LEVEL0_SET_ADRE;
|
||||||
TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
|
TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
|
||||||
HPTWReadE = 1'b1;
|
HPTWRead = 1'b1;
|
||||||
end else begin
|
end else begin
|
||||||
NextWalkerState = FAULT;
|
NextWalkerState = FAULT;
|
||||||
end
|
end
|
||||||
@ -253,7 +254,7 @@ module pagetablewalker
|
|||||||
|
|
||||||
LEVEL0_WDV: begin
|
LEVEL0_WDV: begin
|
||||||
TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
|
TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
|
||||||
HPTWReadE = 1'b1;
|
HPTWRead = 1'b1;
|
||||||
if (HPTWStall) begin
|
if (HPTWStall) begin
|
||||||
NextWalkerState = LEVEL0_WDV;
|
NextWalkerState = LEVEL0_WDV;
|
||||||
end else begin
|
end else begin
|
||||||
@ -281,6 +282,7 @@ module pagetablewalker
|
|||||||
end
|
end
|
||||||
|
|
||||||
FAULT: begin
|
FAULT: begin
|
||||||
|
SelPTW = 1'b0;
|
||||||
NextWalkerState = IDLE;
|
NextWalkerState = IDLE;
|
||||||
WalkerInstrPageFaultF = ~DTLBMissMQ;
|
WalkerInstrPageFaultF = ~DTLBMissMQ;
|
||||||
WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore;
|
WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore;
|
||||||
@ -324,7 +326,9 @@ module pagetablewalker
|
|||||||
|
|
||||||
logic TerapageMisaligned, GigapageMisaligned, BadTerapage, BadGigapage;
|
logic TerapageMisaligned, GigapageMisaligned, BadTerapage, BadGigapage;
|
||||||
|
|
||||||
flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
|
flopenl #(.TYPE(statetype)) WalkerStageReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
|
||||||
|
|
||||||
|
flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState);
|
||||||
|
|
||||||
/* -----\/----- EXCLUDED -----\/-----
|
/* -----\/----- EXCLUDED -----\/-----
|
||||||
assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV ||
|
assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV ||
|
||||||
@ -338,7 +342,7 @@ module pagetablewalker
|
|||||||
always_comb begin
|
always_comb begin
|
||||||
PRegEn = 1'b0;
|
PRegEn = 1'b0;
|
||||||
TranslationPAdr = '0;
|
TranslationPAdr = '0;
|
||||||
HPTWReadE = 1'b0;
|
HPTWRead = 1'b0;
|
||||||
PageTableEntry = '0;
|
PageTableEntry = '0;
|
||||||
PageType = '0;
|
PageType = '0;
|
||||||
DTLBWriteM = '0;
|
DTLBWriteM = '0;
|
||||||
@ -369,7 +373,7 @@ module pagetablewalker
|
|||||||
|
|
||||||
LEVEL3_WDV: begin
|
LEVEL3_WDV: begin
|
||||||
TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000};
|
TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000};
|
||||||
HPTWReadE = 1'b1;
|
HPTWRead = 1'b1;
|
||||||
if (HPTWStall) begin
|
if (HPTWStall) begin
|
||||||
NextWalkerState = LEVEL3_WDV;
|
NextWalkerState = LEVEL3_WDV;
|
||||||
end else begin
|
end else begin
|
||||||
@ -403,7 +407,7 @@ module pagetablewalker
|
|||||||
|
|
||||||
LEVEL2_WDV: begin
|
LEVEL2_WDV: begin
|
||||||
TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
|
TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
|
||||||
HPTWReadE = 1'b1;
|
HPTWRead = 1'b1;
|
||||||
if (HPTWStall) begin
|
if (HPTWStall) begin
|
||||||
NextWalkerState = LEVEL2_WDV;
|
NextWalkerState = LEVEL2_WDV;
|
||||||
end else begin
|
end else begin
|
||||||
@ -437,7 +441,7 @@ module pagetablewalker
|
|||||||
|
|
||||||
LEVEL1_WDV: begin
|
LEVEL1_WDV: begin
|
||||||
TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
|
TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
|
||||||
HPTWReadE = 1'b1;
|
HPTWRead = 1'b1;
|
||||||
if (HPTWStall) begin
|
if (HPTWStall) begin
|
||||||
NextWalkerState = LEVEL1_WDV;
|
NextWalkerState = LEVEL1_WDV;
|
||||||
end else begin
|
end else begin
|
||||||
@ -472,7 +476,7 @@ module pagetablewalker
|
|||||||
|
|
||||||
LEVEL0_WDV: begin
|
LEVEL0_WDV: begin
|
||||||
TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
|
TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
|
||||||
HPTWReadE = 1'b1;
|
HPTWRead = 1'b1;
|
||||||
if (HPTWStall) begin
|
if (HPTWStall) begin
|
||||||
NextWalkerState = LEVEL0_WDV;
|
NextWalkerState = LEVEL0_WDV;
|
||||||
end else begin
|
end else begin
|
||||||
@ -502,6 +506,7 @@ module pagetablewalker
|
|||||||
end
|
end
|
||||||
|
|
||||||
FAULT: begin
|
FAULT: begin
|
||||||
|
SelPTW = 1'b0;
|
||||||
NextWalkerState = IDLE;
|
NextWalkerState = IDLE;
|
||||||
WalkerInstrPageFaultF = ~DTLBMissMQ;
|
WalkerInstrPageFaultF = ~DTLBMissMQ;
|
||||||
WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore;
|
WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore;
|
||||||
@ -550,7 +555,7 @@ module pagetablewalker
|
|||||||
//endgenerate
|
//endgenerate
|
||||||
end else begin
|
end else begin
|
||||||
assign HPTWPAdrE = 0;
|
assign HPTWPAdrE = 0;
|
||||||
assign HPTWReadE = 0;
|
assign HPTWRead = 0;
|
||||||
assign WalkerInstrPageFaultF = 0;
|
assign WalkerInstrPageFaultF = 0;
|
||||||
assign WalkerLoadPageFaultM = 0;
|
assign WalkerLoadPageFaultM = 0;
|
||||||
assign WalkerStorePageFaultM = 0;
|
assign WalkerStorePageFaultM = 0;
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user