mirror of
https://github.com/openhwgroup/cvw
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Merge pull request #918 from jordancarlin/fp_tests_make
Testfloat vector generation refactoring + root Makefile cleanup
This commit is contained in:
David Harris
GitHub
commit
d3621318c0
39
Makefile
39
Makefile
@ -4,45 +4,36 @@
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SIM = ${WALLY}/sim
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all:
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make riscof
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make zsbl
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make testfloat
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# make verify
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make coverage
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# make benchmarks
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.PHONY: all riscof testfloat combined_IF_vectors zsbl benchmarks coremark embench coverage clean
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all: riscof testfloat combined_IF_vectors zsbl coverage # benchmarks
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# riscof builds the riscv-arch-test and wally-riscv-arch-test suites
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riscof:
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make -C sim
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$(MAKE) -C sim
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testfloat:
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cd ${WALLY}/addins/SoftFloat-3e/build/Linux-x86_64-GCC; make
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cd ${WALLY}/addins/TestFloat-3e/build/Linux-x86_64-GCC; make
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cd ${WALLY}/tests/fp; ./create_all_vectors.sh
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$(MAKE) -C ${WALLY}/tests/fp vectors
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combined_IF_vectors: testfloat riscof
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$(MAKE) -C ${WALLY}/tests/fp combined_IF_vectors
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zsbl:
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$(MAKE) -C ${WALLY}/fpga/zsbl
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verify:
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cd ${SIM}; ./regression-wally
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cd ${SIM}/sim; ./sim-testfloat-batch all
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make imperasdv
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benchmarks:
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make coremark
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make embench
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$(MAKE) coremark
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$(MAKE) embench
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coremark:
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cd ${WALLY}/benchmarks/coremark; make; make run
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cd ${WALLY}/benchmarks/coremark; $(MAKE); $(MAKE) run
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embench:
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cd ${WALLY}/benchmarks/embench; make; make run
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cd ${WALLY}/benchmarks/embench; $(MAKE); $(MAKE) run
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coverage:
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make -C tests/coverage
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$(MAKE) -C tests/coverage
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clean:
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make clean -C sim
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$(MAKE) clean -C sim
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$(MAKE) clean -C ${WALLY}/tests/fp
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Binary file not shown.
34
tests/fp/Makefile
Executable file
34
tests/fp/Makefile
Executable file
@ -0,0 +1,34 @@
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# Jordan Carlin, jcarlin@hmc.edu, August 2024
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# Testfloat vector Makefile for CORE-V-Wally
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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SOFTFLOAT_DIR := ${WALLY}/addins/SoftFloat-3e/build/Linux-x86_64-GCC
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TESTFLOAT_DIR := ${WALLY}/addins/TestFloat-3e/build/Linux-x86_64-GCC
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.PHONY: all softfloat testfloat vectors combined_IF_vectors clean
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all: vectors combined_IF_vectors
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softfloat: ${SOFTFLOAT_DIR}/softfloat.a
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testfloat: ${TESTFLOAT_DIR}/testfloat
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vectors: testfloat
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$(MAKE) -C ${WALLY}/tests/fp/vectors
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combined_IF_vectors: ${WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/M/src vectors
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cd ${WALLY}/tests/fp/combined_IF_vectors \
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&& ./create_IF_vectors.sh
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clean:
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$(MAKE) -C ${WALLY}/tests/fp/vectors clean
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rm -f ${WALLY}/tests/fp/combined_IF_vectors/IF_vectors/*.tv
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${SOFTFLOAT_DIR}/softfloat.a:
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$(MAKE) -C ${SOFTFLOAT_DIR}
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${TESTFLOAT_DIR}/testfloat: ${SOFTFLOAT_DIR}/softfloat.a
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$(MAKE) -C ${TESTFLOAT_DIR}
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${WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/M/src:
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@$(error "riscv-arch-tests must be generated first. Run make from $$WALLY")
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@ -1,187 +1,171 @@
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james.stine@okstate.edu 14 Jan 2022
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These are the testvectors (TV) to test the floating-point units using
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These are the testvectors (TV) to test the floating-point unit using
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Berkeley TestFloat written originally by John Hauser. TestFloat
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requires both TestFloat and SoftFloat.
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The locations at time of this README is found here:
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The locations of these tools at time of this README is found here:
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TestFloat-3e: http://www.jhauser.us/arithmetic/TestFloat.html
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SoftFloat-3e: http://www.jhauser.us/arithmetic/SoftFloat.html
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These files have been compiled on a x86_64 environment by going into
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the build/Linux-x86_64-GCC directory and typing make. A script
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createX.sh (e.g., create_vectors32.sh) has been included that create
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the TV for each rounding mode and operation. These scripts must be
|
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run in the build directory of TestFloat.
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These tools have been compiled on a x86_64 environment by going into
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their respective build/Linux-x86_64-GCC directories and running make.
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A set of scripts is also include that runs everything from the
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baseline directory. Please change the BUILD and OUTPUT variable to
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change your baseline program where its compiled and where you want to
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output the vectors. By default, the vectors are output into the
|
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vectors subdirectory.
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The makefile in the vectors subdirectory of this directory will generate TV
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for each rounding mode and operation. It also puts an underscore between each
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vector instead of a space to allow SystemVerilog readmemh to read correctly.
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After each TV has been created a script (included) is run called
|
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undy.sh that puts an underscore between vector to allow SystemVerilog
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readmemh to read correctly.
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./undy.sh file.tv
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To remove all the underscores from all the TV files, one can run the
|
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command that will add underscores appropriately to all the files.
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cd vectors
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../undy.sh \*
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Note: due to size, the fxx_fma_xx.tv vectors are not included.
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However, they can easily be created with the create scripts.
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The makefile at the top level of this directory will compile SoftFloat and
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TestFloat and then generate all of the TVs. It also generates TVs for the
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combined integer floating-point divider.
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Although not needed, a case.sh script is included to change the case
|
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of the hex output. This is for those that do not like to see
|
||||
hexadecimal capitalized :P.
|
||||
hexadecimal capitalized :P.
|
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|
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46464 185856 836352 f16_add_rd.tv
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46464 185856 836352 f16_add_rne.tv
|
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46464 185856 836352 f16_add_ru.tv
|
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46464 185856 836352 f16_add_rz.tv
|
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46464 185856 836352 f16_div_rd.tv
|
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46464 185856 836352 f16_div_rne.tv
|
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46464 185856 836352 f16_div_ru.tv
|
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46464 185856 836352 f16_div_rz.tv
|
||||
46464 185856 836352 f16_mul_rd.tv
|
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46464 185856 836352 f16_mul_rne.tv
|
||||
46464 185856 836352 f16_mul_ru.tv
|
||||
46464 185856 836352 f16_mul_rz.tv
|
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408 1224 5304 f16_sqrt_rd.tv
|
||||
408 1224 5304 f16_sqrt_rne.tv
|
||||
408 1224 5304 f16_sqrt_ru.tv
|
||||
408 1224 5304 f16_sqrt_rz.tv
|
||||
46464 185856 836352 f16_sub_rd.tv
|
||||
46464 185856 836352 f16_sub_rne.tv
|
||||
46464 185856 836352 f16_sub_ru.tv
|
||||
46464 185856 836352 f16_sub_rz.tv
|
||||
46464 185856 1393920 f32_add_rd.tv
|
||||
46464 185856 1393920 f32_add_rne.tv
|
||||
46464 185856 1393920 f32_add_ru.tv
|
||||
46464 185856 1393920 f32_add_rz.tv
|
||||
46464 185856 1068672 f32_cmp_eq_signaling.tv
|
||||
46464 185856 1068672 f32_cmp_eq.tv
|
||||
46464 185856 1068672 f32_cmp_le_quiet.tv
|
||||
46464 185856 1068672 f32_cmp_le.tv
|
||||
46464 185856 1068672 f32_cmp_lt_quiet.tv
|
||||
46464 185856 1068672 f32_cmp_lt.tv
|
||||
46464 185856 1393920 f32_div_rd.tv
|
||||
46464 185856 1393920 f32_div_rne.tv
|
||||
46464 185856 1393920 f32_div_ru.tv
|
||||
46464 185856 1393920 f32_div_rz.tv
|
||||
600 1800 17400 f32_f64_rd.tv
|
||||
600 1800 17400 f32_f64_rne.tv
|
||||
600 1800 17400 f32_f64_ru.tv
|
||||
600 1800 17400 f32_f64_rz.tv
|
||||
600 1800 12600 f32_i32_rd.tv
|
||||
600 1800 12600 f32_i32_rne.tv
|
||||
600 1800 12600 f32_i32_ru.tv
|
||||
600 1800 12600 f32_i32_rz.tv
|
||||
600 1800 17400 f32_i64_rd.tv
|
||||
600 1800 17400 f32_i64_rne.tv
|
||||
600 1800 17400 f32_i64_ru.tv
|
||||
600 1800 17400 f32_i64_rz.tv
|
||||
46464 185856 1393920 f32_mul_rd.tv
|
||||
46464 185856 1393920 f32_mul_rne.tv
|
||||
46464 185856 1393920 f32_mul_ru.tv
|
||||
46464 185856 1393920 f32_mul_rz.tv
|
||||
600 1800 12600 f32_sqrt_rd.tv
|
||||
600 1800 12600 f32_sqrt_rne.tv
|
||||
600 1800 12600 f32_sqrt_ru.tv
|
||||
600 1800 12600 f32_sqrt_rz.tv
|
||||
46464 185856 1393920 f32_sub_rd.tv
|
||||
46464 185856 1393920 f32_sub_rne.tv
|
||||
46464 185856 1393920 f32_sub_ru.tv
|
||||
46464 185856 1393920 f32_sub_rz.tv
|
||||
600 1800 12600 f32_ui32_rd.tv
|
||||
600 1800 12600 f32_ui32_rne.tv
|
||||
600 1800 12600 f32_ui32_ru.tv
|
||||
600 1800 12600 f32_ui32_rz.tv
|
||||
600 1800 17400 f32_ui64_rd.tv
|
||||
600 1800 17400 f32_ui64_rne.tv
|
||||
600 1800 17400 f32_ui64_ru.tv
|
||||
600 1800 17400 f32_ui64_rz.tv
|
||||
46464 185856 2509056 f64_add_rd.tv
|
||||
46464 185856 2509056 f64_add_rne.tv
|
||||
46464 185856 2509056 f64_add_ru.tv
|
||||
46464 185856 2509056 f64_add_rz.tv
|
||||
46464 185856 1812096 f64_cmp_eq_signaling.tv
|
||||
46464 185856 1812096 f64_cmp_eq.tv
|
||||
46464 185856 1812096 f64_cmp_le_quiet.tv
|
||||
46464 185856 1812096 f64_cmp_le.tv
|
||||
46464 185856 1812096 f64_cmp_lt_quiet.tv
|
||||
46464 185856 1812096 f64_cmp_lt.tv
|
||||
46464 185856 2509056 f64_div_rd.tv
|
||||
46464 185856 2509056 f64_div_rne.tv
|
||||
46464 185856 2509056 f64_div_ru.tv
|
||||
46464 185856 2509056 f64_div_rz.tv
|
||||
768 2304 22272 f64_f32_rd.tv
|
||||
768 2304 22272 f64_f32_rne.tv
|
||||
768 2304 22272 f64_f32_ru.tv
|
||||
768 2304 22272 f64_f32_rz.tv
|
||||
768 2304 22272 f64_i32_rd.tv
|
||||
768 2304 22272 f64_i32_rne.tv
|
||||
768 2304 22272 f64_i32_ru.tv
|
||||
768 2304 22272 f64_i32_rz.tv
|
||||
768 2304 28416 f64_i64_rd.tv
|
||||
768 2304 28416 f64_i64_rne.tv
|
||||
768 2304 28416 f64_i64_ru.tv
|
||||
768 2304 28416 f64_i64_rz.tv
|
||||
46464 185856 2509056 f64_mul_rd.tv
|
||||
46464 185856 2509056 f64_mul_rne.tv
|
||||
46464 185856 2509056 f64_mul_ru.tv
|
||||
46464 185856 2509056 f64_mul_rz.tv
|
||||
768 2304 28416 f64_sqrt_rd.tv
|
||||
768 2304 28416 f64_sqrt_rne.tv
|
||||
768 2304 28416 f64_sqrt_ru.tv
|
||||
768 2304 28416 f64_sqrt_rz.tv
|
||||
46464 185856 2509056 f64_sub_rd.tv
|
||||
46464 185856 2509056 f64_sub_rne.tv
|
||||
46464 185856 2509056 f64_sub_ru.tv
|
||||
46464 185856 2509056 f64_sub_rz.tv
|
||||
768 2304 22272 f64_ui32_rd.tv
|
||||
768 2304 22272 f64_ui32_rne.tv
|
||||
768 2304 22272 f64_ui32_ru.tv
|
||||
768 2304 22272 f64_ui32_rz.tv
|
||||
768 2304 28416 f64_ui64_rd.tv
|
||||
768 2304 28416 f64_ui64_rne.tv
|
||||
768 2304 28416 f64_ui64_ru.tv
|
||||
768 2304 28416 f64_ui64_rz.tv
|
||||
372 1116 7812 i32_f32_rd.tv
|
||||
372 1116 7812 i32_f32_rne.tv
|
||||
372 1116 7812 i32_f32_ru.tv
|
||||
372 1116 7812 i32_f32_rz.tv
|
||||
372 1116 10788 i32_f64_rd.tv
|
||||
372 1116 10788 i32_f64_rne.tv
|
||||
372 1116 10788 i32_f64_ru.tv
|
||||
372 1116 10788 i32_f64_rz.tv
|
||||
756 2268 21924 i64_f32_rd.tv
|
||||
756 2268 21924 i64_f32_rne.tv
|
||||
756 2268 21924 i64_f32_ru.tv
|
||||
756 2268 21924 i64_f32_rz.tv
|
||||
756 2268 27972 i64_f64_rd.tv
|
||||
756 2268 27972 i64_f64_rne.tv
|
||||
756 2268 27972 i64_f64_ru.tv
|
||||
756 2268 27972 i64_f64_rz.tv
|
||||
372 1116 7812 ui32_f32_rd.tv
|
||||
372 1116 7812 ui32_f32_rne.tv
|
||||
372 1116 7812 ui32_f32_ru.tv
|
||||
372 1116 7812 ui32_f32_rz.tv
|
||||
372 1116 10788 ui32_f64_rd.tv
|
||||
372 1116 10788 ui32_f64_rne.tv
|
||||
372 1116 10788 ui32_f64_ru.tv
|
||||
372 1116 10788 ui32_f64_rz.tv
|
||||
756 2268 21924 ui64_f32_rd.tv
|
||||
756 2268 21924 ui64_f32_rne.tv
|
||||
756 2268 21924 ui64_f32_ru.tv
|
||||
756 2268 21924 ui64_f32_rz.tv
|
||||
756 2268 27972 ui64_f64_rd.tv
|
||||
756 2268 27972 ui64_f64_rne.tv
|
||||
756 2268 27972 ui64_f64_ru.tv
|
||||
756 2268 27972 ui64_f64_rz.tv
|
||||
2840352 11308896 94651296 total
|
||||
46464 185856 836352 f16_add_rd.tv
|
||||
46464 185856 836352 f16_add_rne.tv
|
||||
46464 185856 836352 f16_add_ru.tv
|
||||
46464 185856 836352 f16_add_rz.tv
|
||||
46464 185856 836352 f16_div_rd.tv
|
||||
46464 185856 836352 f16_div_rne.tv
|
||||
46464 185856 836352 f16_div_ru.tv
|
||||
46464 185856 836352 f16_div_rz.tv
|
||||
46464 185856 836352 f16_mul_rd.tv
|
||||
46464 185856 836352 f16_mul_rne.tv
|
||||
46464 185856 836352 f16_mul_ru.tv
|
||||
46464 185856 836352 f16_mul_rz.tv
|
||||
408 1224 5304 f16_sqrt_rd.tv
|
||||
408 1224 5304 f16_sqrt_rne.tv
|
||||
408 1224 5304 f16_sqrt_ru.tv
|
||||
408 1224 5304 f16_sqrt_rz.tv
|
||||
46464 185856 836352 f16_sub_rd.tv
|
||||
46464 185856 836352 f16_sub_rne.tv
|
||||
46464 185856 836352 f16_sub_ru.tv
|
||||
46464 185856 836352 f16_sub_rz.tv
|
||||
46464 185856 1393920 f32_add_rd.tv
|
||||
46464 185856 1393920 f32_add_rne.tv
|
||||
46464 185856 1393920 f32_add_ru.tv
|
||||
46464 185856 1393920 f32_add_rz.tv
|
||||
46464 185856 1068672 f32_cmp_eq_signaling.tv
|
||||
46464 185856 1068672 f32_cmp_eq.tv
|
||||
46464 185856 1068672 f32_cmp_le_quiet.tv
|
||||
46464 185856 1068672 f32_cmp_le.tv
|
||||
46464 185856 1068672 f32_cmp_lt_quiet.tv
|
||||
46464 185856 1068672 f32_cmp_lt.tv
|
||||
46464 185856 1393920 f32_div_rd.tv
|
||||
46464 185856 1393920 f32_div_rne.tv
|
||||
46464 185856 1393920 f32_div_ru.tv
|
||||
46464 185856 1393920 f32_div_rz.tv
|
||||
600 1800 17400 f32_f64_rd.tv
|
||||
600 1800 17400 f32_f64_rne.tv
|
||||
600 1800 17400 f32_f64_ru.tv
|
||||
600 1800 17400 f32_f64_rz.tv
|
||||
600 1800 12600 f32_i32_rd.tv
|
||||
600 1800 12600 f32_i32_rne.tv
|
||||
600 1800 12600 f32_i32_ru.tv
|
||||
600 1800 12600 f32_i32_rz.tv
|
||||
600 1800 17400 f32_i64_rd.tv
|
||||
600 1800 17400 f32_i64_rne.tv
|
||||
600 1800 17400 f32_i64_ru.tv
|
||||
600 1800 17400 f32_i64_rz.tv
|
||||
46464 185856 1393920 f32_mul_rd.tv
|
||||
46464 185856 1393920 f32_mul_rne.tv
|
||||
46464 185856 1393920 f32_mul_ru.tv
|
||||
46464 185856 1393920 f32_mul_rz.tv
|
||||
600 1800 12600 f32_sqrt_rd.tv
|
||||
600 1800 12600 f32_sqrt_rne.tv
|
||||
600 1800 12600 f32_sqrt_ru.tv
|
||||
600 1800 12600 f32_sqrt_rz.tv
|
||||
46464 185856 1393920 f32_sub_rd.tv
|
||||
46464 185856 1393920 f32_sub_rne.tv
|
||||
46464 185856 1393920 f32_sub_ru.tv
|
||||
46464 185856 1393920 f32_sub_rz.tv
|
||||
600 1800 12600 f32_ui32_rd.tv
|
||||
600 1800 12600 f32_ui32_rne.tv
|
||||
600 1800 12600 f32_ui32_ru.tv
|
||||
600 1800 12600 f32_ui32_rz.tv
|
||||
600 1800 17400 f32_ui64_rd.tv
|
||||
600 1800 17400 f32_ui64_rne.tv
|
||||
600 1800 17400 f32_ui64_ru.tv
|
||||
600 1800 17400 f32_ui64_rz.tv
|
||||
46464 185856 2509056 f64_add_rd.tv
|
||||
46464 185856 2509056 f64_add_rne.tv
|
||||
46464 185856 2509056 f64_add_ru.tv
|
||||
46464 185856 2509056 f64_add_rz.tv
|
||||
46464 185856 1812096 f64_cmp_eq_signaling.tv
|
||||
46464 185856 1812096 f64_cmp_eq.tv
|
||||
46464 185856 1812096 f64_cmp_le_quiet.tv
|
||||
46464 185856 1812096 f64_cmp_le.tv
|
||||
46464 185856 1812096 f64_cmp_lt_quiet.tv
|
||||
46464 185856 1812096 f64_cmp_lt.tv
|
||||
46464 185856 2509056 f64_div_rd.tv
|
||||
46464 185856 2509056 f64_div_rne.tv
|
||||
46464 185856 2509056 f64_div_ru.tv
|
||||
46464 185856 2509056 f64_div_rz.tv
|
||||
768 2304 22272 f64_f32_rd.tv
|
||||
768 2304 22272 f64_f32_rne.tv
|
||||
768 2304 22272 f64_f32_ru.tv
|
||||
768 2304 22272 f64_f32_rz.tv
|
||||
768 2304 22272 f64_i32_rd.tv
|
||||
768 2304 22272 f64_i32_rne.tv
|
||||
768 2304 22272 f64_i32_ru.tv
|
||||
768 2304 22272 f64_i32_rz.tv
|
||||
768 2304 28416 f64_i64_rd.tv
|
||||
768 2304 28416 f64_i64_rne.tv
|
||||
768 2304 28416 f64_i64_ru.tv
|
||||
768 2304 28416 f64_i64_rz.tv
|
||||
46464 185856 2509056 f64_mul_rd.tv
|
||||
46464 185856 2509056 f64_mul_rne.tv
|
||||
46464 185856 2509056 f64_mul_ru.tv
|
||||
46464 185856 2509056 f64_mul_rz.tv
|
||||
768 2304 28416 f64_sqrt_rd.tv
|
||||
768 2304 28416 f64_sqrt_rne.tv
|
||||
768 2304 28416 f64_sqrt_ru.tv
|
||||
768 2304 28416 f64_sqrt_rz.tv
|
||||
46464 185856 2509056 f64_sub_rd.tv
|
||||
46464 185856 2509056 f64_sub_rne.tv
|
||||
46464 185856 2509056 f64_sub_ru.tv
|
||||
46464 185856 2509056 f64_sub_rz.tv
|
||||
768 2304 22272 f64_ui32_rd.tv
|
||||
768 2304 22272 f64_ui32_rne.tv
|
||||
768 2304 22272 f64_ui32_ru.tv
|
||||
768 2304 22272 f64_ui32_rz.tv
|
||||
768 2304 28416 f64_ui64_rd.tv
|
||||
768 2304 28416 f64_ui64_rne.tv
|
||||
768 2304 28416 f64_ui64_ru.tv
|
||||
768 2304 28416 f64_ui64_rz.tv
|
||||
372 1116 7812 i32_f32_rd.tv
|
||||
372 1116 7812 i32_f32_rne.tv
|
||||
372 1116 7812 i32_f32_ru.tv
|
||||
372 1116 7812 i32_f32_rz.tv
|
||||
372 1116 10788 i32_f64_rd.tv
|
||||
372 1116 10788 i32_f64_rne.tv
|
||||
372 1116 10788 i32_f64_ru.tv
|
||||
372 1116 10788 i32_f64_rz.tv
|
||||
756 2268 21924 i64_f32_rd.tv
|
||||
756 2268 21924 i64_f32_rne.tv
|
||||
756 2268 21924 i64_f32_ru.tv
|
||||
756 2268 21924 i64_f32_rz.tv
|
||||
756 2268 27972 i64_f64_rd.tv
|
||||
756 2268 27972 i64_f64_rne.tv
|
||||
756 2268 27972 i64_f64_ru.tv
|
||||
756 2268 27972 i64_f64_rz.tv
|
||||
372 1116 7812 ui32_f32_rd.tv
|
||||
372 1116 7812 ui32_f32_rne.tv
|
||||
372 1116 7812 ui32_f32_ru.tv
|
||||
372 1116 7812 ui32_f32_rz.tv
|
||||
372 1116 10788 ui32_f64_rd.tv
|
||||
372 1116 10788 ui32_f64_rne.tv
|
||||
372 1116 10788 ui32_f64_ru.tv
|
||||
372 1116 10788 ui32_f64_rz.tv
|
||||
756 2268 21924 ui64_f32_rd.tv
|
||||
756 2268 21924 ui64_f32_rne.tv
|
||||
756 2268 21924 ui64_f32_ru.tv
|
||||
756 2268 21924 ui64_f32_rz.tv
|
||||
756 2268 27972 ui64_f64_rd.tv
|
||||
756 2268 27972 ui64_f64_rne.tv
|
||||
756 2268 27972 ui64_f64_ru.tv
|
||||
756 2268 27972 ui64_f64_rz.tv
|
||||
2840352 11308896 94651296 total
|
||||
|
||||
|
||||
@ -1,8 +0,0 @@
|
||||
#!/bin/sh
|
||||
|
||||
mkdir -p vectors
|
||||
./create_vectors.sh
|
||||
./remove_spaces.sh
|
||||
|
||||
# to create tvs for evaluation of combined IFdivsqrt
|
||||
cd combined_IF_vectors; ./create_IF_vectors.sh
|
||||
@ -1,483 +0,0 @@
|
||||
#!/bin/sh
|
||||
BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC"
|
||||
OUTPUT="./vectors"
|
||||
echo "Creating ui32_to_f16 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui32_to_f16 > $OUTPUT/ui32_to_f16_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui32_to_f16 > $OUTPUT/ui32_to_f16_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui32_to_f16 > $OUTPUT/ui32_to_f16_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui32_to_f16 > $OUTPUT/ui32_to_f16_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui32_to_f16 > $OUTPUT/ui32_to_f16_rnm.tv
|
||||
echo "Creating ui32_to_f32 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui32_to_f32 > $OUTPUT/ui32_to_f32_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui32_to_f32 > $OUTPUT/ui32_to_f32_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui32_to_f32 > $OUTPUT/ui32_to_f32_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui32_to_f32 > $OUTPUT/ui32_to_f32_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui32_to_f32 > $OUTPUT/ui32_to_f32_rnm.tv
|
||||
echo "Creating ui32_to_f64 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui32_to_f64 > $OUTPUT/ui32_to_f64_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui32_to_f64 > $OUTPUT/ui32_to_f64_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui32_to_f64 > $OUTPUT/ui32_to_f64_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui32_to_f64 > $OUTPUT/ui32_to_f64_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui32_to_f64 > $OUTPUT/ui32_to_f64_rnm.tv
|
||||
echo "Creating ui32_to_f128 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui32_to_f128 > $OUTPUT/ui32_to_f128_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui32_to_f128 > $OUTPUT/ui32_to_f128_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui32_to_f128 > $OUTPUT/ui32_to_f128_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui32_to_f128 > $OUTPUT/ui32_to_f128_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui32_to_f128 > $OUTPUT/ui32_to_f128_rnm.tv
|
||||
echo "Creating ui64_to_f16 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui64_to_f16 > $OUTPUT/ui64_to_f16_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui64_to_f16 > $OUTPUT/ui64_to_f16_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui64_to_f16 > $OUTPUT/ui64_to_f16_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui64_to_f16 > $OUTPUT/ui64_to_f16_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui64_to_f16 > $OUTPUT/ui64_to_f16_rnm.tv
|
||||
echo "Creating ui64_to_f32 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui64_to_f32 > $OUTPUT/ui64_to_f32_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui64_to_f32 > $OUTPUT/ui64_to_f32_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui64_to_f32 > $OUTPUT/ui64_to_f32_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui64_to_f32 > $OUTPUT/ui64_to_f32_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui64_to_f32 > $OUTPUT/ui64_to_f32_rnm.tv
|
||||
echo "Creating ui64_to_f64 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui64_to_f64 > $OUTPUT/ui64_to_f64_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui64_to_f64 > $OUTPUT/ui64_to_f64_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui64_to_f64 > $OUTPUT/ui64_to_f64_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui64_to_f64 > $OUTPUT/ui64_to_f64_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui64_to_f64 > $OUTPUT/ui64_to_f64_rnm.tv
|
||||
echo "Creating ui64_to_f128 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui64_to_f128 > $OUTPUT/ui64_to_f128_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui64_to_f128 > $OUTPUT/ui64_to_f128_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui64_to_f128 > $OUTPUT/ui64_to_f128_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui64_to_f128 > $OUTPUT/ui64_to_f128_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui64_to_f128 > $OUTPUT/ui64_to_f128_rnm.tv
|
||||
echo "Creating i32_to_f16 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i32_to_f16 > $OUTPUT/i32_to_f16_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i32_to_f16 > $OUTPUT/i32_to_f16_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax i32_to_f16 > $OUTPUT/i32_to_f16_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin i32_to_f16 > $OUTPUT/i32_to_f16_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i32_to_f16 > $OUTPUT/i32_to_f16_rnm.tv
|
||||
echo "Creating i32_to_f32 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i32_to_f32 > $OUTPUT/i32_to_f32_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i32_to_f32 > $OUTPUT/i32_to_f32_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax i32_to_f32 > $OUTPUT/i32_to_f32_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin i32_to_f32 > $OUTPUT/i32_to_f32_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i32_to_f32 > $OUTPUT/i32_to_f32_rnm.tv
|
||||
echo "Creating i32_to_f64 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i32_to_f64 > $OUTPUT/i32_to_f64_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i32_to_f64 > $OUTPUT/i32_to_f64_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax i32_to_f64 > $OUTPUT/i32_to_f64_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin i32_to_f64 > $OUTPUT/i32_to_f64_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i32_to_f64 > $OUTPUT/i32_to_f64_rnm.tv
|
||||
echo "Creating i32_to_f128 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i32_to_f128 > $OUTPUT/i32_to_f128_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i32_to_f128 > $OUTPUT/i32_to_f128_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax i32_to_f128 > $OUTPUT/i32_to_f128_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin i32_to_f128 > $OUTPUT/i32_to_f128_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i32_to_f128 > $OUTPUT/i32_to_f128_rnm.tv
|
||||
echo "Creating i64_to_f16 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i64_to_f16 > $OUTPUT/i64_to_f16_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i64_to_f16 > $OUTPUT/i64_to_f16_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax i64_to_f16 > $OUTPUT/i64_to_f16_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin i64_to_f16 > $OUTPUT/i64_to_f16_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i64_to_f16 > $OUTPUT/i64_to_f16_rnm.tv
|
||||
echo "Creating i64_to_f32 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i64_to_f32 > $OUTPUT/i64_to_f32_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i64_to_f32 > $OUTPUT/i64_to_f32_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax i64_to_f32 > $OUTPUT/i64_to_f32_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin i64_to_f32 > $OUTPUT/i64_to_f32_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i64_to_f32 > $OUTPUT/i64_to_f32_rnm.tv
|
||||
echo "Creating i64_to_f64 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i64_to_f64 > $OUTPUT/i64_to_f64_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i64_to_f64 > $OUTPUT/i64_to_f64_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax i64_to_f64 > $OUTPUT/i64_to_f64_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin i64_to_f64 > $OUTPUT/i64_to_f64_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i64_to_f64 > $OUTPUT/i64_to_f64_rnm.tv
|
||||
echo "Creating i64_to_f128 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i64_to_f128 > $OUTPUT/i64_to_f128_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i64_to_f128 > $OUTPUT/i64_to_f128_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax i64_to_f128 > $OUTPUT/i64_to_f128_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin i64_to_f128 > $OUTPUT/i64_to_f128_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i64_to_f128 > $OUTPUT/i64_to_f128_rnm.tv
|
||||
echo "Creating f16_to_ui32 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f16_to_ui32 > $OUTPUT/f16_to_ui32_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f16_to_ui32 > $OUTPUT/f16_to_ui32_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f16_to_ui32 > $OUTPUT/f16_to_ui32_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f16_to_ui32 > $OUTPUT/f16_to_ui32_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f16_to_ui32 > $OUTPUT/f16_to_ui32_rnm.tv
|
||||
echo "Creating f32_to_ui32 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f32_to_ui32 > $OUTPUT/f32_to_ui32_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f32_to_ui32 > $OUTPUT/f32_to_ui32_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f32_to_ui32 > $OUTPUT/f32_to_ui32_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f32_to_ui32 > $OUTPUT/f32_to_ui32_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f32_to_ui32 > $OUTPUT/f32_to_ui32_rnm.tv
|
||||
echo "Creating f64_to_ui32 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f64_to_ui32 > $OUTPUT/f64_to_ui32_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f64_to_ui32 > $OUTPUT/f64_to_ui32_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f64_to_ui32 > $OUTPUT/f64_to_ui32_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f64_to_ui32 > $OUTPUT/f64_to_ui32_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f64_to_ui32 > $OUTPUT/f64_to_ui32_rnm.tv
|
||||
echo "Creating f128_to_ui32 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f128_to_ui32 > $OUTPUT/f128_to_ui32_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f128_to_ui32 > $OUTPUT/f128_to_ui32_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f128_to_ui32 > $OUTPUT/f128_to_ui32_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f128_to_ui32 > $OUTPUT/f128_to_ui32_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f128_to_ui32 > $OUTPUT/f128_to_ui32_rnm.tv
|
||||
echo "Creating f16_to_ui64 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f16_to_ui64 > $OUTPUT/f16_to_ui64_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f16_to_ui64 > $OUTPUT/f16_to_ui64_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f16_to_ui64 > $OUTPUT/f16_to_ui64_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f16_to_ui64 > $OUTPUT/f16_to_ui64_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f16_to_ui64 > $OUTPUT/f16_to_ui64_rnm.tv
|
||||
echo "Creating f32_to_ui64 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f32_to_ui64 > $OUTPUT/f32_to_ui64_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f32_to_ui64 > $OUTPUT/f32_to_ui64_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f32_to_ui64 > $OUTPUT/f32_to_ui64_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f32_to_ui64 > $OUTPUT/f32_to_ui64_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f32_to_ui64 > $OUTPUT/f32_to_ui64_rnm.tv
|
||||
echo "Creating f64_to_ui64 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f64_to_ui64 > $OUTPUT/f64_to_ui64_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f64_to_ui64 > $OUTPUT/f64_to_ui64_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f64_to_ui64 > $OUTPUT/f64_to_ui64_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f64_to_ui64 > $OUTPUT/f64_to_ui64_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f64_to_ui64 > $OUTPUT/f64_to_ui64_rnm.tv
|
||||
echo "Creating f128_to_ui64 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f128_to_ui64 > $OUTPUT/f128_to_ui64_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f128_to_ui64 > $OUTPUT/f128_to_ui64_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f128_to_ui64 > $OUTPUT/f128_to_ui64_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f128_to_ui64 > $OUTPUT/f128_to_ui64_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f128_to_ui64 > $OUTPUT/f128_to_ui64_rnm.tv
|
||||
echo "Creating f16_to_i32 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f16_to_i32 > $OUTPUT/f16_to_i32_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f16_to_i32 > $OUTPUT/f16_to_i32_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f16_to_i32 > $OUTPUT/f16_to_i32_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f16_to_i32 > $OUTPUT/f16_to_i32_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f16_to_i32 > $OUTPUT/f16_to_i32_rnm.tv
|
||||
echo "Creating f32_to_i32 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f32_to_i32 > $OUTPUT/f32_to_i32_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f32_to_i32 > $OUTPUT/f32_to_i32_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f32_to_i32 > $OUTPUT/f32_to_i32_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f32_to_i32 > $OUTPUT/f32_to_i32_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f32_to_i32 > $OUTPUT/f32_to_i32_rnm.tv
|
||||
echo "Creating f64_to_i32 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f64_to_i32 > $OUTPUT/f64_to_i32_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f64_to_i32 > $OUTPUT/f64_to_i32_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f64_to_i32 > $OUTPUT/f64_to_i32_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f64_to_i32 > $OUTPUT/f64_to_i32_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f64_to_i32 > $OUTPUT/f64_to_i32_rnm.tv
|
||||
echo "Creating f128_to_i32 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f128_to_i32 > $OUTPUT/f128_to_i32_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f128_to_i32 > $OUTPUT/f128_to_i32_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f128_to_i32 > $OUTPUT/f128_to_i32_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f128_to_i32 > $OUTPUT/f128_to_i32_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f128_to_i32 > $OUTPUT/f128_to_i32_rnm.tv
|
||||
echo "Creating f16_to_i64 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f16_to_i64 > $OUTPUT/f16_to_i64_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f16_to_i64 > $OUTPUT/f16_to_i64_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f16_to_i64 > $OUTPUT/f16_to_i64_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f16_to_i64 > $OUTPUT/f16_to_i64_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f16_to_i64 > $OUTPUT/f16_to_i64_rnm.tv
|
||||
echo "Creating f32_to_i64 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f32_to_i64 > $OUTPUT/f32_to_i64_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f32_to_i64 > $OUTPUT/f32_to_i64_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f32_to_i64 > $OUTPUT/f32_to_i64_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f32_to_i64 > $OUTPUT/f32_to_i64_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f32_to_i64 > $OUTPUT/f32_to_i64_rnm.tv
|
||||
echo "Creating f64_to_i64 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f64_to_i64 > $OUTPUT/f64_to_i64_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f64_to_i64 > $OUTPUT/f64_to_i64_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f64_to_i64 > $OUTPUT/f64_to_i64_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f64_to_i64 > $OUTPUT/f64_to_i64_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f64_to_i64 > $OUTPUT/f64_to_i64_rnm.tv
|
||||
echo "Creating f128_to_i64 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f128_to_i64 > $OUTPUT/f128_to_i64_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f128_to_i64 > $OUTPUT/f128_to_i64_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f128_to_i64 > $OUTPUT/f128_to_i64_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f128_to_i64 > $OUTPUT/f128_to_i64_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f128_to_i64 > $OUTPUT/f128_to_i64_rnm.tv
|
||||
echo "Creating f16_to_f32 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f16_to_f32 > $OUTPUT/f16_to_f32_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f16_to_f32 > $OUTPUT/f16_to_f32_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f16_to_f32 > $OUTPUT/f16_to_f32_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f16_to_f32 > $OUTPUT/f16_to_f32_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f16_to_f32 > $OUTPUT/f16_to_f32_rnm.tv
|
||||
echo "Creating f16_to_f64 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f16_to_f64 > $OUTPUT/f16_to_f64_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f16_to_f64 > $OUTPUT/f16_to_f64_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f16_to_f64 > $OUTPUT/f16_to_f64_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f16_to_f64 > $OUTPUT/f16_to_f64_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f16_to_f64 > $OUTPUT/f16_to_f64_rnm.tv
|
||||
echo "Creating f16_to_f128 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f16_to_f128 > $OUTPUT/f16_to_f128_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f16_to_f128 > $OUTPUT/f16_to_f128_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f16_to_f128 > $OUTPUT/f16_to_f128_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f16_to_f128 > $OUTPUT/f16_to_f128_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f16_to_f128 > $OUTPUT/f16_to_f128_rnm.tv
|
||||
echo "Creating f32_to_f16 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f32_to_f16 > $OUTPUT/f32_to_f16_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f32_to_f16 > $OUTPUT/f32_to_f16_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f32_to_f16 > $OUTPUT/f32_to_f16_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f32_to_f16 > $OUTPUT/f32_to_f16_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f32_to_f16 > $OUTPUT/f32_to_f16_rnm.tv
|
||||
echo "Creating f32_to_f64 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f32_to_f64 > $OUTPUT/f32_to_f64_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f32_to_f64 > $OUTPUT/f32_to_f64_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f32_to_f64 > $OUTPUT/f32_to_f64_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f32_to_f64 > $OUTPUT/f32_to_f64_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f32_to_f64 > $OUTPUT/f32_to_f64_rnm.tv
|
||||
echo "Creating f32_to_f128 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f32_to_f128 > $OUTPUT/f32_to_f128_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f32_to_f128 > $OUTPUT/f32_to_f128_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f32_to_f128 > $OUTPUT/f32_to_f128_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f32_to_f128 > $OUTPUT/f32_to_f128_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f32_to_f128 > $OUTPUT/f32_to_f128_rnm.tv
|
||||
echo "Creating f64_to_f16 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f64_to_f16 > $OUTPUT/f64_to_f16_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f64_to_f16 > $OUTPUT/f64_to_f16_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f64_to_f16 > $OUTPUT/f64_to_f16_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f64_to_f16 > $OUTPUT/f64_to_f16_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f64_to_f16 > $OUTPUT/f64_to_f16_rnm.tv
|
||||
echo "Creating f64_to_f32 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f64_to_f32 > $OUTPUT/f64_to_f32_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f64_to_f32 > $OUTPUT/f64_to_f32_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f64_to_f32 > $OUTPUT/f64_to_f32_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f64_to_f32 > $OUTPUT/f64_to_f32_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f64_to_f32 > $OUTPUT/f64_to_f32_rnm.tv
|
||||
echo "Creating f64_to_f128 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f64_to_f128 > $OUTPUT/f64_to_f128_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f64_to_f128 > $OUTPUT/f64_to_f128_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f64_to_f128 > $OUTPUT/f64_to_f128_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f64_to_f128 > $OUTPUT/f64_to_f128_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f64_to_f128 > $OUTPUT/f64_to_f128_rnm.tv
|
||||
echo "Creating f128_to_f16 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f128_to_f16 > $OUTPUT/f128_to_f16_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f128_to_f16 > $OUTPUT/f128_to_f16_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f128_to_f16 > $OUTPUT/f128_to_f16_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f128_to_f16 > $OUTPUT/f128_to_f16_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f128_to_f16 > $OUTPUT/f128_to_f16_rnm.tv
|
||||
echo "Creating f128_to_f32 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f128_to_f32 > $OUTPUT/f128_to_f32_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f128_to_f32 > $OUTPUT/f128_to_f32_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f128_to_f32 > $OUTPUT/f128_to_f32_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f128_to_f32 > $OUTPUT/f128_to_f32_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f128_to_f32 > $OUTPUT/f128_to_f32_rnm.tv
|
||||
echo "Creating f128_to_f64 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f128_to_f64 > $OUTPUT/f128_to_f64_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f128_to_f64 > $OUTPUT/f128_to_f64_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f128_to_f64 > $OUTPUT/f128_to_f64_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f128_to_f64 > $OUTPUT/f128_to_f64_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f128_to_f64 > $OUTPUT/f128_to_f64_rnm.tv
|
||||
echo "Creating f16_add vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_add > $OUTPUT/f16_add_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_add > $OUTPUT/f16_add_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_add > $OUTPUT/f16_add_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_add > $OUTPUT/f16_add_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_add > $OUTPUT/f16_add_rnm.tv
|
||||
echo "Creating f32_add vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_add > $OUTPUT/f32_add_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_add > $OUTPUT/f32_add_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_add > $OUTPUT/f32_add_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_add > $OUTPUT/f32_add_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_add > $OUTPUT/f32_add_rnm.tv
|
||||
echo "Creating f64_add vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_add > $OUTPUT/f64_add_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_add > $OUTPUT/f64_add_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_add > $OUTPUT/f64_add_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_add > $OUTPUT/f64_add_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_add > $OUTPUT/f64_add_rnm.tv
|
||||
echo "Creating f128_add vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_add > $OUTPUT/f128_add_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_add > $OUTPUT/f128_add_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_add > $OUTPUT/f128_add_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_add > $OUTPUT/f128_add_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_add > $OUTPUT/f128_add_rnm.tv
|
||||
echo "Creating f16_sub vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_sub > $OUTPUT/f16_sub_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_sub > $OUTPUT/f16_sub_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_sub > $OUTPUT/f16_sub_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_sub > $OUTPUT/f16_sub_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_sub > $OUTPUT/f16_sub_rnm.tv
|
||||
echo "Creating f32_sub vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_sub > $OUTPUT/f32_sub_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_sub > $OUTPUT/f32_sub_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_sub > $OUTPUT/f32_sub_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_sub > $OUTPUT/f32_sub_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_sub > $OUTPUT/f32_sub_rnm.tv
|
||||
echo "Creating f64_sub vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_sub > $OUTPUT/f64_sub_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_sub > $OUTPUT/f64_sub_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_sub > $OUTPUT/f64_sub_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_sub > $OUTPUT/f64_sub_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_sub > $OUTPUT/f64_sub_rnm.tv
|
||||
echo "Creating f128_sub vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_sub > $OUTPUT/f128_sub_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_sub > $OUTPUT/f128_sub_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_sub > $OUTPUT/f128_sub_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_sub > $OUTPUT/f128_sub_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_sub > $OUTPUT/f128_sub_rnm.tv
|
||||
echo "Creating f16_mul vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_mul > $OUTPUT/f16_mul_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_mul > $OUTPUT/f16_mul_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_mul > $OUTPUT/f16_mul_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_mul > $OUTPUT/f16_mul_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_mul > $OUTPUT/f16_mul_rnm.tv
|
||||
echo "Creating f32_mul vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_mul > $OUTPUT/f32_mul_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_mul > $OUTPUT/f32_mul_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_mul > $OUTPUT/f32_mul_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_mul > $OUTPUT/f32_mul_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_mul > $OUTPUT/f32_mul_rnm.tv
|
||||
echo "Creating f64_mul vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_mul > $OUTPUT/f64_mul_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_mul > $OUTPUT/f64_mul_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_mul > $OUTPUT/f64_mul_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_mul > $OUTPUT/f64_mul_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_mul > $OUTPUT/f64_mul_rnm.tv
|
||||
echo "Creating f128_mul vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_mul > $OUTPUT/f128_mul_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_mul > $OUTPUT/f128_mul_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_mul > $OUTPUT/f128_mul_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_mul > $OUTPUT/f128_mul_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_mul > $OUTPUT/f128_mul_rnm.tv
|
||||
echo "Creating f16_div vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_div > $OUTPUT/f16_div_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_div > $OUTPUT/f16_div_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_div > $OUTPUT/f16_div_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_div > $OUTPUT/f16_div_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_div > $OUTPUT/f16_div_rnm.tv
|
||||
echo "Creating f32_div vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_div > $OUTPUT/f32_div_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_div > $OUTPUT/f32_div_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_div > $OUTPUT/f32_div_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_div > $OUTPUT/f32_div_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_div > $OUTPUT/f32_div_rnm.tv
|
||||
echo "Creating f64_div vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_div > $OUTPUT/f64_div_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_div > $OUTPUT/f64_div_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_div > $OUTPUT/f64_div_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_div > $OUTPUT/f64_div_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_div > $OUTPUT/f64_div_rnm.tv
|
||||
echo "Creating f128_div vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_div > $OUTPUT/f128_div_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_div > $OUTPUT/f128_div_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_div > $OUTPUT/f128_div_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_div > $OUTPUT/f128_div_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_div > $OUTPUT/f128_div_rnm.tv
|
||||
echo "Creating f16_sqrt vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f16_sqrt > $OUTPUT/f16_sqrt_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f16_sqrt > $OUTPUT/f16_sqrt_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f16_sqrt > $OUTPUT/f16_sqrt_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f16_sqrt > $OUTPUT/f16_sqrt_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f16_sqrt > $OUTPUT/f16_sqrt_rnm.tv
|
||||
echo "Creating f32_sqrt vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f32_sqrt > $OUTPUT/f32_sqrt_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f32_sqrt > $OUTPUT/f32_sqrt_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f32_sqrt > $OUTPUT/f32_sqrt_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f32_sqrt > $OUTPUT/f32_sqrt_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f32_sqrt > $OUTPUT/f32_sqrt_rnm.tv
|
||||
echo "Creating f64_sqrt vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f64_sqrt > $OUTPUT/f64_sqrt_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f64_sqrt > $OUTPUT/f64_sqrt_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f64_sqrt > $OUTPUT/f64_sqrt_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f64_sqrt > $OUTPUT/f64_sqrt_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f64_sqrt > $OUTPUT/f64_sqrt_rnm.tv
|
||||
echo "Creating f128_sqrt vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f128_sqrt > $OUTPUT/f128_sqrt_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f128_sqrt > $OUTPUT/f128_sqrt_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f128_sqrt > $OUTPUT/f128_sqrt_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f128_sqrt > $OUTPUT/f128_sqrt_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f128_sqrt > $OUTPUT/f128_sqrt_rnm.tv
|
||||
echo "Creating f16_eq vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_eq > $OUTPUT/f16_eq_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_eq > $OUTPUT/f16_eq_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_eq > $OUTPUT/f16_eq_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_eq > $OUTPUT/f16_eq_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_eq > $OUTPUT/f16_eq_rnm.tv
|
||||
echo "Creating f32_eq vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_eq > $OUTPUT/f32_eq_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_eq > $OUTPUT/f32_eq_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_eq > $OUTPUT/f32_eq_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_eq > $OUTPUT/f32_eq_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_eq > $OUTPUT/f32_eq_rnm.tv
|
||||
echo "Creating f64_eq vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_eq > $OUTPUT/f64_eq_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_eq > $OUTPUT/f64_eq_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_eq > $OUTPUT/f64_eq_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_eq > $OUTPUT/f64_eq_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_eq > $OUTPUT/f64_eq_rnm.tv
|
||||
echo "Creating f128_eq vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_eq > $OUTPUT/f128_eq_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_eq > $OUTPUT/f128_eq_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_eq > $OUTPUT/f128_eq_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_eq > $OUTPUT/f128_eq_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_eq > $OUTPUT/f128_eq_rnm.tv
|
||||
echo "Creating f16_le vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_le > $OUTPUT/f16_le_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_le > $OUTPUT/f16_le_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_le > $OUTPUT/f16_le_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_le > $OUTPUT/f16_le_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_le > $OUTPUT/f16_le_rnm.tv
|
||||
echo "Creating f32_le vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_le > $OUTPUT/f32_le_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_le > $OUTPUT/f32_le_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_le > $OUTPUT/f32_le_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_le > $OUTPUT/f32_le_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_le > $OUTPUT/f32_le_rnm.tv
|
||||
echo "Creating f64_le vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_le > $OUTPUT/f64_le_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_le > $OUTPUT/f64_le_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_le > $OUTPUT/f64_le_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_le > $OUTPUT/f64_le_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_le > $OUTPUT/f64_le_rnm.tv
|
||||
echo "Creating f128_le vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_le > $OUTPUT/f128_le_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_le > $OUTPUT/f128_le_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_le > $OUTPUT/f128_le_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_le > $OUTPUT/f128_le_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_le > $OUTPUT/f128_le_rnm.tv
|
||||
echo "Creating f16_lt vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_lt > $OUTPUT/f16_lt_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_lt > $OUTPUT/f16_lt_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_lt > $OUTPUT/f16_lt_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_lt > $OUTPUT/f16_lt_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_lt > $OUTPUT/f16_lt_rnm.tv
|
||||
echo "Creating f32_lt vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_lt > $OUTPUT/f32_lt_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_lt > $OUTPUT/f32_lt_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_lt > $OUTPUT/f32_lt_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_lt > $OUTPUT/f32_lt_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_lt > $OUTPUT/f32_lt_rnm.tv
|
||||
echo "Creating f64_lt vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_lt > $OUTPUT/f64_lt_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_lt > $OUTPUT/f64_lt_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_lt > $OUTPUT/f64_lt_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_lt > $OUTPUT/f64_lt_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_lt > $OUTPUT/f64_lt_rnm.tv
|
||||
echo "Creating f128_lt vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_lt > $OUTPUT/f128_lt_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_lt > $OUTPUT/f128_lt_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_lt > $OUTPUT/f128_lt_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_lt > $OUTPUT/f128_lt_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_lt > $OUTPUT/f128_lt_rnm.tv
|
||||
echo "Creating f16_mulAdd vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_mulAdd > $OUTPUT/f16_mulAdd_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_mulAdd > $OUTPUT/f16_mulAdd_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_mulAdd > $OUTPUT/f16_mulAdd_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_mulAdd > $OUTPUT/f16_mulAdd_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_mulAdd > $OUTPUT/f16_mulAdd_rnm.tv
|
||||
echo "Creating f32_mulAdd vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_mulAdd > $OUTPUT/f32_mulAdd_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_mulAdd > $OUTPUT/f32_mulAdd_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_mulAdd > $OUTPUT/f32_mulAdd_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_mulAdd > $OUTPUT/f32_mulAdd_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_mulAdd > $OUTPUT/f32_mulAdd_rnm.tv
|
||||
echo "Creating f64_mulAdd vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_mulAdd > $OUTPUT/f64_mulAdd_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_mulAdd > $OUTPUT/f64_mulAdd_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_mulAdd > $OUTPUT/f64_mulAdd_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_mulAdd > $OUTPUT/f64_mulAdd_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_mulAdd > $OUTPUT/f64_mulAdd_rnm.tv
|
||||
echo "Creating f128_mulAdd vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_mulAdd > $OUTPUT/f128_mulAdd_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_mulAdd > $OUTPUT/f128_mulAdd_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_mulAdd > $OUTPUT/f128_mulAdd_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_mulAdd > $OUTPUT/f128_mulAdd_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_mulAdd > $OUTPUT/f128_mulAdd_rnm.tv
|
||||
@ -1,483 +0,0 @@
|
||||
#!/bin/sh
|
||||
BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC"
|
||||
OUTPUT="./vectors"
|
||||
echo "Editing ui32_to_f16 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_rnm.tv
|
||||
echo "Editing ui32_to_f32 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_rnm.tv
|
||||
echo "Editing ui32_to_f64 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_rnm.tv
|
||||
echo "Editing ui32_to_f128 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_rnm.tv
|
||||
echo "Editing ui64_to_f16 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_rnm.tv
|
||||
echo "Editing ui64_to_f32 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_rnm.tv
|
||||
echo "Editing ui64_to_f64 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_rnm.tv
|
||||
echo "Editing ui64_to_f128 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_rnm.tv
|
||||
echo "Editing i32_to_f16 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f16_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f16_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f16_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f16_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f16_rnm.tv
|
||||
echo "Editing i32_to_f32 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f32_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f32_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f32_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f32_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f32_rnm.tv
|
||||
echo "Editing i32_to_f64 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f64_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f64_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f64_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f64_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f64_rnm.tv
|
||||
echo "Editing i32_to_f128 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f128_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f128_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f128_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f128_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f128_rnm.tv
|
||||
echo "Editing i64_to_f16 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f16_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f16_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f16_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f16_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f16_rnm.tv
|
||||
echo "Editing i64_to_f32 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f32_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f32_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f32_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f32_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f32_rnm.tv
|
||||
echo "Editing i64_to_f64 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f64_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f64_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f64_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f64_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f64_rnm.tv
|
||||
echo "Editing i64_to_f128 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f128_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f128_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f128_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f128_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f128_rnm.tv
|
||||
echo "Editing f16_to_ui32 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_rnm.tv
|
||||
echo "Editing f32_to_ui32 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_rnm.tv
|
||||
echo "Editing f64_to_ui32 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_rnm.tv
|
||||
echo "Editing f128_to_ui32 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_rnm.tv
|
||||
echo "Editing f16_to_ui64 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_rnm.tv
|
||||
echo "Editing f32_to_ui64 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_rnm.tv
|
||||
echo "Editing f64_to_ui64 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_rnm.tv
|
||||
echo "Editing f128_to_ui64 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_rnm.tv
|
||||
echo "Editing f16_to_i32 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_i32_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_i32_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_i32_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_i32_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_i32_rnm.tv
|
||||
echo "Editing f32_to_i32 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_i32_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_i32_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_i32_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_i32_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_i32_rnm.tv
|
||||
echo "Editing f64_to_i32 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_i32_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_i32_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_i32_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_i32_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_i32_rnm.tv
|
||||
echo "Editing f128_to_i32 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_i32_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_i32_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_i32_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_i32_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_i32_rnm.tv
|
||||
echo "Editing f16_to_i64 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_i64_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_i64_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_i64_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_i64_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_i64_rnm.tv
|
||||
echo "Editing f32_to_i64 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_i64_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_i64_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_i64_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_i64_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_i64_rnm.tv
|
||||
echo "Editing f64_to_i64 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_i64_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_i64_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_i64_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_i64_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_i64_rnm.tv
|
||||
echo "Editing f128_to_i64 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_i64_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_i64_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_i64_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_i64_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_i64_rnm.tv
|
||||
echo "Editing f16_to_f32 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_f32_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_f32_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_f32_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_f32_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_f32_rnm.tv
|
||||
echo "Editing f16_to_f64 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_f64_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_f64_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_f64_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_f64_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_f64_rnm.tv
|
||||
echo "Editing f16_to_f128 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_f128_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_f128_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_f128_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_f128_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_f128_rnm.tv
|
||||
echo "Editing f32_to_f16 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_f16_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_f16_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_f16_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_f16_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_f16_rnm.tv
|
||||
echo "Editing f32_to_f64 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_f64_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_f64_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_f64_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_f64_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_f64_rnm.tv
|
||||
echo "Editing f32_to_f128 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_f128_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_f128_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_f128_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_f128_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_f128_rnm.tv
|
||||
echo "Editing f64_to_f16 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_f16_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_f16_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_f16_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_f16_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_f16_rnm.tv
|
||||
echo "Editing f64_to_f32 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_f32_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_f32_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_f32_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_f32_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_f32_rnm.tv
|
||||
echo "Editing f64_to_f128 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_f128_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_f128_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_f128_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_f128_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_f128_rnm.tv
|
||||
echo "Editing f128_to_f16 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_f16_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_f16_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_f16_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_f16_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_f16_rnm.tv
|
||||
echo "Editing f128_to_f32 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_f32_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_f32_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_f32_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_f32_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_f32_rnm.tv
|
||||
echo "Editing f128_to_f64 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_f64_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_f64_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_f64_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_f64_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_f64_rnm.tv
|
||||
echo "Editing f16_add test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_add_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_add_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_add_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_add_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_add_rnm.tv
|
||||
echo "Editing f32_add test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_add_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_add_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_add_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_add_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_add_rnm.tv
|
||||
echo "Editing f64_add test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_add_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_add_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_add_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_add_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_add_rnm.tv
|
||||
echo "Editing f128_add test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_add_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_add_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_add_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_add_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_add_rnm.tv
|
||||
echo "Editing f16_sub test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_sub_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_sub_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_sub_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_sub_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_sub_rnm.tv
|
||||
echo "Editing f32_sub test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_sub_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_sub_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_sub_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_sub_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_sub_rnm.tv
|
||||
echo "Editing f64_sub test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_sub_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_sub_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_sub_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_sub_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_sub_rnm.tv
|
||||
echo "Editing f128_sub test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_sub_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_sub_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_sub_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_sub_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_sub_rnm.tv
|
||||
echo "Editing f16_mul test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_mul_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_mul_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_mul_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_mul_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_mul_rnm.tv
|
||||
echo "Editing f32_mul test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_mul_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_mul_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_mul_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_mul_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_mul_rnm.tv
|
||||
echo "Editing f64_mul test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_mul_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_mul_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_mul_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_mul_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_mul_rnm.tv
|
||||
echo "Editing f128_mul test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_mul_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_mul_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_mul_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_mul_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_mul_rnm.tv
|
||||
echo "Editing f16_div test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_div_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_div_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_div_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_div_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_div_rnm.tv
|
||||
echo "Editing f32_div test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_div_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_div_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_div_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_div_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_div_rnm.tv
|
||||
echo "Editing f64_div test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_div_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_div_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_div_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_div_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_div_rnm.tv
|
||||
echo "Editing f128_div test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_div_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_div_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_div_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_div_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_div_rnm.tv
|
||||
echo "Editing f16_sqrt test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_sqrt_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_sqrt_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_sqrt_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_sqrt_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_sqrt_rnm.tv
|
||||
echo "Editing f32_sqrt test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_sqrt_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_sqrt_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_sqrt_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_sqrt_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_sqrt_rnm.tv
|
||||
echo "Editing f64_sqrt test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_sqrt_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_sqrt_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_sqrt_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_sqrt_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_sqrt_rnm.tv
|
||||
echo "Editing f128_sqrt test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_sqrt_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_sqrt_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_sqrt_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_sqrt_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_sqrt_rnm.tv
|
||||
echo "Editing f16_eq test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_eq_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_eq_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_eq_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_eq_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_eq_rnm.tv
|
||||
echo "Editing f32_eq test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_eq_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_eq_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_eq_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_eq_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_eq_rnm.tv
|
||||
echo "Editing f64_eq test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_eq_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_eq_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_eq_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_eq_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_eq_rnm.tv
|
||||
echo "Editing f128_eq test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_eq_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_eq_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_eq_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_eq_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_eq_rnm.tv
|
||||
echo "Editing f16_le test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_le_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_le_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_le_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_le_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_le_rnm.tv
|
||||
echo "Editing f32_le test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_le_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_le_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_le_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_le_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_le_rnm.tv
|
||||
echo "Editing f64_le test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_le_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_le_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_le_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_le_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_le_rnm.tv
|
||||
echo "Editing f128_le test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_le_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_le_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_le_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_le_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_le_rnm.tv
|
||||
echo "Editing f16_lt test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_lt_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_lt_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_lt_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_lt_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_lt_rnm.tv
|
||||
echo "Editing f32_lt test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_lt_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_lt_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_lt_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_lt_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_lt_rnm.tv
|
||||
echo "Editing f64_lt test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_lt_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_lt_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_lt_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_lt_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_lt_rnm.tv
|
||||
echo "Editing f128_lt test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_lt_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_lt_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_lt_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_lt_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_lt_rnm.tv
|
||||
echo "Editing f16_mulAdd test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rnm.tv
|
||||
echo "Editing f32_mulAdd test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rnm.tv
|
||||
echo "Editing f64_mulAdd test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rnm.tv
|
||||
echo "Editing f128_mulAdd test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rnm.tv
|
||||
81
tests/fp/vectors/Makefile
Executable file
81
tests/fp/vectors/Makefile
Executable file
@ -0,0 +1,81 @@
|
||||
.DELETE_ON_ERROR:
|
||||
SHELL := /bin/bash
|
||||
|
||||
TESTFLOAT_DIR := ${WALLY}/addins/TestFloat-3e/build/Linux-x86_64-GCC
|
||||
TESTFLOAT_GEN_CMD := ${TESTFLOAT_DIR}/testfloat_gen -tininessafter -level
|
||||
|
||||
# List of testvectors to generate. Each rounding mode will be generated for each test.
|
||||
convert := ui32_to_f16 ui32_to_f32 ui32_to_f64 ui32_to_f128 \
|
||||
ui64_to_f16 ui64_to_f32 ui64_to_f64 ui64_to_f128 \
|
||||
i32_to_f16 i32_to_f32 i32_to_f64 i32_to_f128 \
|
||||
i64_to_f16 i64_to_f32 i64_to_f64 i64_to_f128 \
|
||||
f16_to_ui32 f32_to_ui32 f64_to_ui32 f128_to_ui32 \
|
||||
f16_to_ui64 f32_to_ui64 f64_to_ui64 f128_to_ui64 \
|
||||
f16_to_i32 f32_to_i32 f64_to_i32 f128_to_i32 \
|
||||
f16_to_i64 f32_to_i64 f64_to_i64 f128_to_i64 \
|
||||
f16_to_f32 f16_to_f64 f16_to_f128 \
|
||||
f32_to_f16 f32_to_f64 f32_to_f128 \
|
||||
f64_to_f16 f64_to_f32 f64_to_f128 \
|
||||
f128_to_f16 f128_to_f32 f128_to_f64
|
||||
add := f16_add f32_add f64_add f128_add
|
||||
sub := f16_sub f32_sub f64_sub f128_sub
|
||||
mul := f16_mul f32_mul f64_mul f128_mul
|
||||
div := f16_div f32_div f64_div f128_div
|
||||
sqrt := f16_sqrt f32_sqrt f64_sqrt f128_sqrt
|
||||
eq := f16_eq f32_eq f64_eq f128_eq
|
||||
le := f16_le f32_le f64_le f128_le
|
||||
lt := f16_lt f32_lt f64_lt f128_lt
|
||||
mulAdd := f16_mulAdd f32_mulAdd f64_mulAdd f128_mulAdd
|
||||
|
||||
tests := $(convert) $(add) $(sub) $(mul) $(div) $(sqrt) $(eq) $(le) $(lt) $(mulAdd)
|
||||
|
||||
|
||||
.PHONY: all rne rz ru rd rnm clean
|
||||
|
||||
all: rne rz ru rd rnm
|
||||
|
||||
# Generate test vectors for each rounding mode
|
||||
rne: $(addsuffix _rne.tv, $(tests))
|
||||
rz: $(addsuffix _rz.tv, $(tests))
|
||||
ru: $(addsuffix _ru.tv, $(tests))
|
||||
rd: $(addsuffix _rd.tv, $(tests))
|
||||
rnm: $(addsuffix _rnm.tv, $(tests))
|
||||
|
||||
# Rules to generate individual test vectors, broken up by rounding mode
|
||||
%_rne.tv: ${TESTFLOAT_GEN}
|
||||
@echo Creating $*_rne.tv vectors
|
||||
@if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi ; \
|
||||
${TESTFLOAT_GEN_CMD} $$level -rnear_even $* > $@
|
||||
@sed -i 's/ /_/g' $@
|
||||
|
||||
%_rz.tv: ${TESTFLOAT_GEN}
|
||||
@echo Creating $*_rz.tv vectors
|
||||
@if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi ; \
|
||||
${TESTFLOAT_GEN_CMD} $$level -rminMag $* > $@
|
||||
@sed -i 's/ /_/g' $@
|
||||
|
||||
%_ru.tv: ${TESTFLOAT_GEN}
|
||||
@echo Creating $*_ru.tv vectors
|
||||
@if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi ; \
|
||||
${TESTFLOAT_GEN_CMD} $$level -rmax $* > $@
|
||||
@sed -i 's/ /_/g' $@
|
||||
|
||||
%_rd.tv: ${TESTFLOAT_GEN}
|
||||
@echo Creating $*_rd.tv vectors
|
||||
@if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi ; \
|
||||
${TESTFLOAT_GEN_CMD} $$level -rmin $* > $@
|
||||
@sed -i 's/ /_/g' $@
|
||||
|
||||
%_rnm.tv: ${TESTFLOAT_GEN}
|
||||
@echo Creating $*_rnm.tv vectors
|
||||
@if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi ; \
|
||||
${TESTFLOAT_GEN_CMD} $$level -rnear_maxMag $* > $@
|
||||
@sed -i 's/ /_/g' $@
|
||||
|
||||
# Generate TestFloat first if necessary
|
||||
${TESTFLOAT_GEN}:
|
||||
$(MAKE) -C ${WALLY}/tests/fp testfloat
|
||||
|
||||
clean:
|
||||
rm -f *.tv
|
||||
rm -f sed*
|
||||
Loading…
Reference in New Issue
Block a user