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dtim writes are supressed on non cacheable operation.

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This commit is contained in:
Ross Thompson 2022-03-12 00:46:11 -06:00
parent d8947fa616
commit d347de8c49
3 changed files with 21 additions and 20 deletions
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2
pipelined/src/ifu/ifu.sv
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@ -177,7 +177,7 @@ module ifu (
dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM(PCPF[31:0]), .IEUAdrE(PCNextFSpill), dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM(PCPF[31:0]), .IEUAdrE(PCNextFSpill),
.TrapM(1'b0), .FinalWriteDataM(), .ByteMaskM('0), .TrapM(1'b0), .FinalWriteDataM(), .ByteMaskM('0),
.ReadDataWordM(FinalInstrRawF), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead), .ReadDataWordM(FinalInstrRawF), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead),
.BusCommittedM(), .DCacheStallM(ICacheStallF), .BusCommittedM(), .DCacheStallM(ICacheStallF), .Cacheable(CacheableF),
.DCacheCommittedM(), .DCacheMiss(ICacheMiss), .DCacheAccess(ICacheAccess)); .DCacheCommittedM(), .DCacheMiss(ICacheMiss), .DCacheAccess(ICacheAccess));
end end

37
pipelined/src/lsu/dtim.sv
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@ -30,28 +30,29 @@
`include "wally-config.vh" `include "wally-config.vh"
module dtim( module dtim(
input logic clk, reset, input logic clk, reset,
input logic CPUBusy, input logic CPUBusy,
input logic [1:0] LSURWM, input logic [1:0] LSURWM,
input logic [`XLEN-1:0] IEUAdrM, input logic [`XLEN-1:0] IEUAdrM,
input logic [`XLEN-1:0] IEUAdrE, input logic [`XLEN-1:0] IEUAdrE,
input logic TrapM, input logic TrapM,
input logic [`XLEN-1:0] FinalWriteDataM, input logic [`XLEN-1:0] FinalWriteDataM,
input logic [`XLEN/8-1:0] ByteMaskM, input logic [`XLEN/8-1:0] ByteMaskM,
output logic [`XLEN-1:0] ReadDataWordM, input logic Cacheable,
output logic BusStall, output logic [`XLEN-1:0] ReadDataWordM,
output logic LSUBusWrite, output logic BusStall,
output logic LSUBusRead, output logic LSUBusWrite,
output logic BusCommittedM, output logic LSUBusRead,
output logic DCacheStallM, output logic BusCommittedM,
output logic DCacheCommittedM, output logic DCacheStallM,
output logic DCacheMiss, output logic DCacheCommittedM,
output logic DCacheAccess); output logic DCacheMiss,
output logic DCacheAccess);
simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram ( simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
.clk, .ByteMask(ByteMaskM), .clk, .ByteMask(ByteMaskM),
.a(CPUBusy | LSURWM[0] | reset ? IEUAdrM[31:0] : IEUAdrE[31:0]), // move mux out; this shouldn't be needed when stails are handled differently *** .a(CPUBusy | LSURWM[0] | reset ? IEUAdrM[31:0] : IEUAdrE[31:0]), // move mux out; this shouldn't be needed when stails are handled differently ***
.we(LSURWM[0] & ~TrapM), // have to ignore write if Trap. .we(LSURWM[0] & Cacheable & ~TrapM), // have to ignore write if Trap.
.wd(FinalWriteDataM), .rd(ReadDataWordM)); .wd(FinalWriteDataM), .rd(ReadDataWordM));
// since we have a local memory the bus connections are all disabled. // since we have a local memory the bus connections are all disabled.

2
pipelined/src/lsu/lsu.sv
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@ -192,7 +192,7 @@ module lsu (
// Merge SimpleRAM and SRAM1p1rw into one that is good for synthesis and RAM libraries and flops // Merge SimpleRAM and SRAM1p1rw into one that is good for synthesis and RAM libraries and flops
dtim dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .FinalWriteDataM, dtim dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .FinalWriteDataM,
.ReadDataWordM, .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM, .ReadDataWordM, .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM,
.DCacheStallM, .DCacheCommittedM, .ByteMaskM, .DCacheStallM, .DCacheCommittedM, .ByteMaskM, .Cacheable(CacheableM),
.DCacheMiss, .DCacheAccess); .DCacheMiss, .DCacheAccess);
end end
if (`DBUS) begin : bus if (`DBUS) begin : bus