diff --git a/src/rvvi/packetizer.sv b/src/rvvi/packetizer.sv
index 00f394ab5..3cf465268 100644
--- a/src/rvvi/packetizer.sv
+++ b/src/rvvi/packetizer.sv
@@ -85,6 +85,8 @@ module packetizer import cvw::*; #(parameter cvw_t P,
   logic [15:0]             Length;
   logic [TotalFrameLengthBits-1:0] TotalFrame;
   logic [31:0] TotalFrameWords [TotalFrameLengthBytes/4-1:0];
+
+  logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvviDelay;
   
   typedef enum              {STATE_RDY, STATE_WAIT, STATE_TRANS, STATE_TRANS_DONE} statetype;
   statetype CurrState, NextState;
@@ -111,6 +113,8 @@ module packetizer import cvw::*; #(parameter cvw_t P,
   assign WordCountEnable = (CurrState == STATE_RDY & valid) | (CurrState == STATE_TRANS & TransReady);
   assign WordCountReset = CurrState == STATE_RDY;
 
+  flopenr #(187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)) rvvireg(m_axi_aclk, ~m_axi_aresetn, valid, rvvi, rvviDelay);
+
 
   counter #(10) WordCounter(m_axi_aclk, WordCountReset, WordCountEnable, WordCount);
   // *** BUG BytesInFrame will eventually depend on the length of the data stored into the ethernet frame
@@ -130,7 +134,7 @@ module packetizer import cvw::*; #(parameter cvw_t P,
     assign TotalFrameWords[index] = TotalFrame[(index*32)+32-1 : (index*32)];
   end
 
-  assign TotalFrame = {rvvi, Length, Tag, DstMac, SrcMac};
+  assign TotalFrame = {rvviDelay, Length, Tag, DstMac, SrcMac};
 
   // *** fix me later
   assign SrcMac = 48'h8F54_0000_1654; // made something up
diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv
index bb9516435..75265ab29 100644
--- a/src/wally/wallypipelinedsoc.sv
+++ b/src/wally/wallypipelinedsoc.sv
@@ -99,6 +99,10 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P)  (
 
   rvvisynth #(P, MAX_CSRS) rvvisynth(.clk, .reset, .valid, .rvvi);
 
+  // a bunch of these signals would be needed for the xilinx ethernet IP
+  // but I switched to using https://github.com/alexforencich/verilog-ethernet
+  // so most arn't needed anymore.  *** remove once I've confirmed this
+  // works in synthesis.
   logic [3:0]                                       m_axi_awid;
   logic [12:0]                                      m_axi_awaddr;
   logic [7:0]                                       m_axi_awlen;
@@ -140,8 +144,6 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P)  (
   
   logic                                             tx_error_underflow, tx_fifo_overflow, tx_fifo_bad_frame, tx_fifo_good_frame, rx_error_bad_frame;
   logic                                             rx_error_bad_fcs, rx_fifo_overflow, rx_fifo_bad_frame, rx_fifo_good_frame;
-  
-  
 
   packetizer #(P, MAX_CSRS) packetizer(.rvvi, .valid, .m_axi_aclk(clk), .m_axi_aresetn(~reset), .RVVIStall,
     .m_axi_awid, .m_axi_awaddr, .m_axi_awlen, .m_axi_awsize, .m_axi_awburst, .m_axi_awcache, .m_axi_awvalid,
@@ -171,10 +173,6 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P)  (
     .cfg_ifg(8'd12), .cfg_tx_enable(1'b1), .cfg_rx_enable(1'b1)
     );
   
-
-
-  // *** finally fake the axi4 interface
   assign m_axi_awready = '1;
-  //assign m_axi_wready = '1;
   
 endmodule