diff --git a/config/derivlist.txt b/config/derivlist.txt index 7e6cd6909..a82339cfc 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -444,6 +444,7 @@ DCACHE_SUPPORTED 0 VIRTMEM_SUPPORTED 0 ZICBOM_SUPPORTED 0 ZICBOZ_SUPPORTED 0 +ZICCLSM_SUPPORTED 0 SVPBMT_SUPPORTED 0 SVNAPOT_SUPPORTED 0 ZAAMO_SUPPORTED 0 @@ -455,6 +456,7 @@ DCACHE_SUPPORTED 0 VIRTMEM_SUPPORTED 0 ZICBOM_SUPPORTED 0 ZICBOZ_SUPPORTED 0 +ZICCLSM_SUPPORTED 0 SVPBMT_SUPPORTED 0 SVNAPOT_SUPPORTED 0 ZAAMO_SUPPORTED 0 diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index 39e174412..ba876f6b7 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -5,6 +5,9 @@ // This file is needed in the config subdirectory for each config supporting coverage. // It defines which extensions are enabled for that config. +// Define XLEN, used in covergroups +`define XLEN32 1 + // Unprivileged extensions `include "RV32I_coverage.svh" `include "RV32M_coverage.svh" diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index 0ab6f76a7..901616311 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -5,6 +5,9 @@ // This file is needed in the config subdirectory for each config supporting coverage. // It defines which extensions are enabled for that config. +// Define XLEN, used in covergroups +`define XLEN64 1 + // Unprivileged extensions `include "RV64I_coverage.svh" `include "RV64M_coverage.svh" diff --git a/src/fpu/fcmp.sv b/src/fpu/fcmp.sv index d1baac3b8..682e492be 100755 --- a/src/fpu/fcmp.sv +++ b/src/fpu/fcmp.sv @@ -75,6 +75,7 @@ module fcmp import cvw::*; #(parameter cvw_t P) ( 3'b0?1: if (P.ZFA_SUPPORTED) CmpNV = Zfa ? EitherSNaN : EitherNaN; // fltq,fleq / flt,fle perform CompareQuietLess / CompareSignalingLess differing on when to set invalid else CmpNV = EitherNaN; // flt, fle + 3'b100: CmpNV = 1'b0; default: CmpNV = 1'bx; endcase end diff --git a/src/fpu/fround.sv b/src/fpu/fround.sv index b5c1b975e..2814c766b 100644 --- a/src/fpu/fround.sv +++ b/src/fpu/fround.sv @@ -146,7 +146,8 @@ module fround import cvw::*; #(parameter cvw_t P) ( packoutput #(P) packoutput(W, Fmt, FRound); // pack and NaN-box based on selected format. // Flags - assign FRoundNV = XSNaN; // invalid if input is signaling NaN - assign FRoundNX = ZfaFRoundNX & ~EgeNf & (Rp | Tp); // Inexact if Round or Sticky bit set for FRoundNX instruction + assign FRoundNV = XSNaN; // invalid if input is signaling NaN + assign FRoundNX = ZfaFRoundNX & ~EgeNf & (Rp | Tp) & ~XNaN; // Inexact if Round or Sticky bit set for FRoundNX instruction + // Note: NX must not be raised if input is invalid endmodule diff --git a/tests/coverage/WALLY-init-lib.h b/tests/coverage/WALLY-init-lib.h index dd29bbab8..59245bb2c 100644 --- a/tests/coverage/WALLY-init-lib.h +++ b/tests/coverage/WALLY-init-lib.h @@ -7,20 +7,20 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw -// +// // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You // may obtain a copy of the License at // // https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// @@ -28,12 +28,6 @@ // The PMP tests are sensitive to the exact addresses in this code, so unfortunately // modifying anything breaks those tests. -// Provides simple firmware services through ecall. Place argument in a0 and issue ecall: -// 0: change to user mode -// 1: change to supervisor mode -// 3: change to machine mode -// 4: terminate program - .section .text.init .global rvtest_entry_point @@ -47,21 +41,21 @@ rvtest_entry_point: csrw medeleg, zero # Don't delegate exceptions # li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again # li t1, 0x02004000 # MTIMECMP in CLINT -# sd t0, 0(t1) - li t0, 0x80 -# li t0, 0x00 +# sd t0, 0(t1) + li t0, 0x80 +# li t0, 0x00 csrw mie, t0 # Enable machine timer interrupt - la t0, topoftrapstack + la t0, topoftrapstack csrw mscratch, t0 # MSCRATCH holds trap stack pointer csrsi mstatus, 0x8 # Turn on mstatus.MIE global interrupt enable # set up PMP so user and supervisor mode can access full address space csrw pmpcfg0, 0xF # configure PMP0 to TOR RWX - li t0, 0xFFFFFFFF + li t0, 0xFFFFFFFF csrw pmpaddr0, t0 # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses j main # Call main function in user test program done: - li a0, 4 # argument to finish program + li a0, 4 # argument to finish program ecall # system call to finish program j self_loop # wait forever (not taken) @@ -75,11 +69,11 @@ trap_handler: csrr t1, mtval # And the trap value bgez t0, exception # if msb is clear, it is an exception -interrupt: # must be a timer interrupt +interrupt: # must be a timer interrupt li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again li t1, 0x02004000 # MTIMECMP in CLIN - sd t0, 0(t1) - csrw stimecmp, t0 # sets stimecmp to big number so it doesnt interrupt + sd t0, 0(t1) + csrw stimecmp, t0 # sets stimecmp to big number so it doesnt interrupt li t0, 32 csrc sip, t0 # clears stimer interrupt j trap_return # clean up and return @@ -105,7 +99,7 @@ changeprivilege: trap_return: # return from trap handler csrr t0, mepc # get address of instruction that caused exception - li t1, 0x20000 + li t1, 0x20000 csrs mstatus, t1 # set mprv bit to fetch instruction with permission of code that trapped lh t0, 0(t0) # get instruction that caused exception csrc mstatus, t1 # clear mprv bit to restore normal operation @@ -133,20 +127,8 @@ write_tohost: self_loop: j self_loop # wait - -// utility routines - -# put a 1 in msb of a0 (position XLEN-1); works for both RV32 and RV64 -setmsb: - li a0, 0x80000000 # 1 in bit 31 - slli a1, a0, 1 # check if register is wider than 31 bits - beqz a1, setmsbdone # yes, a0 has 1 in bit 31 - slli a0, a0, 16 # no: shift a0 to have 1 inn bit 63 - slli a0, a0, 16 # use two shifts of 16 bits each to be compatible with compiling either RV32 or 64 -setmsbdone: - ret # return to calller - -.section .tohost + +.section .tohost tohost: # write to HTIF .dword 0 fromhost: @@ -154,20 +136,17 @@ fromhost: .EQU XLEN,64 begin_signature: - .fill 6*(XLEN/32),4,0xdeadbeef # + .fill 6*(XLEN/32),4,0xdeadbeef # end_signature: -scratch: - .fill 4,4,0x0 - # Initialize stack with room for 512 bytes .bss .space 512 topofstack: # And another stack for the trap handler -.bss +.bss .space 512 topoftrapstack: .align 4 -.section .text.main +.section .text.main \ No newline at end of file